fre Project Status
Project File: fre.ise Current State: Translated
Module Name: fre
  • Errors:
 
Target Device: xc3s400-4pq208
  • Warnings:
 
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
fre Partition Summary [-]
No partition information was found.
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 15 3584 0%
Number of Slice Flip Flops 27 7168 0%
Number of 4 input LUTs 26 7168 0%
Number of bonded IOBs 10 141 7%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent水 10 11 11:13:00 2006   
Translation ReportCurrent水 10 11 11:13:04 2006   
Map Report     
Place and Route ReportCurrent水 10 11 11:13:08 2006   
Static Timing ReportCurrent水 10 11 11:13:10 2006   
Bitgen ReportCurrent水 10 11 11:13:16 2006   

Date Generated: 10/25/2010 - 18:36:29
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