Design Overview for test

PropertyValue
Project Name:d:\xilinx\myproject\xilinxsamples_v2.0\3s400changed\part_three\s16_sdram\part2\project
Target Device:xc3s400
Report Generated:Friday 10/19/07 at 10:45
Printable Summary (View as HTML)test_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:417,1681% 
Number of 4 input LUTs:687,1681% 
Logic Distribution:    
Number of occupied Slices:593,5841% 
Number of Slices containing only related logic:5959100% 
Number of Slices containing unrelated logic:0590% 
Total Number of 4 input LUTs:687,1681% 
Number of bonded IOBs:6614146% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentFriday 10/19/07 at 10:44
Translation ReportCurrentFriday 10/19/07 at 10:45
Map ReportCurrentFriday 10/19/07 at 10:45
Pad ReportCurrentFriday 10/19/07 at 10:45
Place and Route ReportCurrentFriday 10/19/07 at 10:45
Post Place and Route Static Timing ReportCurrentFriday 10/19/07 at 10:45
Bitgen ReportCurrentFriday 10/19/07 at 10:45