Design Overview for slavefifo_wr

PropertyValue
Project Name:d:\xilinx\myproject\3s400_slavefifo
Target Device:xc3s400
Report Generated:Friday 12/07/07 at 16:01
Printable Summary (View as HTML)slavefifo_wr_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:377,1681% 
Number of 4 input LUTs:717,1681% 
Logic Distribution:    
Number of occupied Slices:483,5841% 
Number of Slices containing only related logic:4848100% 
Number of Slices containing unrelated logic:0480% 
Total Number 4 input LUTs:907,1681% 
Number used as logic:71   
Number used as a route-thru:19   
Number of bonded IOBs:1514110% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentFriday 12/07/07 at 15:59
Translation ReportCurrentFriday 12/07/07 at 16:01
Map ReportCurrentFriday 12/07/07 at 16:01
Pad ReportCurrentFriday 12/07/07 at 16:01
Place and Route ReportCurrentFriday 12/07/07 at 16:01
Post Place and Route Static Timing ReportCurrentFriday 12/07/07 at 16:01
Bitgen ReportCurrentFriday 12/07/07 at 16:01