Design Overview for sram_test

PropertyValue
Project Name:d:\try\examples\s11_sram_control\sram
Target Device:xc3s400
Report Generated:Tuesday 10/10/06 at 17:13
Printable Summary (View as HTML)sram_test_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:597,1681% 
Number of 4 input LUTs:757,1681% 
Logic Distribution:    
Number of occupied Slices:643,5841% 
Number of Slices containing only related logic:6464100% 
Number of Slices containing unrelated logic:0640% 
Total Number 4 input LUTs:1227,1681% 
Number used as logic:75   
Number used as a route-thru:47   
Number of bonded IOBs:5414138% 
Number of GCLKs:2825% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentTuesday 10/10/06 at 17:01
Translation ReportCurrentTuesday 10/10/06 at 17:12
Map ReportCurrentTuesday 10/10/06 at 17:12
Pad ReportCurrentTuesday 10/10/06 at 17:12
Place and Route ReportCurrentTuesday 10/10/06 at 17:12
Post Place and Route Static Timing ReportCurrentTuesday 10/10/06 at 17:12
Bitgen ReportCurrentTuesday 10/10/06 at 17:13