Property | Value |
Project Name: | d:\try\3s400changed\part_two\s9_vga\part2\project |
Target Device: | xc3s400 |
Report Generated: | Wednesday 10/11/06 at 23:48 |
Printable Summary (View as HTML) | vga_pong_top_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers: | 191 | 7,168 | 2% | |
Number used as Flip Flops: | 187 | |||
Number used as Latches: | 4 | |||
Number of 4 input LUTs: | 599 | 7,168 | 8% | |
Logic Distribution: | ||||
Number of occupied Slices: | 406 | 3,584 | 11% | |
Number of Slices containing only related logic: | 406 | 406 | 100% | |
Number of Slices containing unrelated logic: | 0 | 406 | 0% | |
Total Number 4 input LUTs: | 738 | 7,168 | 10% | |
Number used as logic: | 599 | |||
Number used as a route-thru: | 139 | |||
Number of bonded IOBs: | 16 | 141 | 11% | |
Number of GCLKs: | 1 | 8 | 12% |
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Thursday 04/27/06 at 09:29 |
Translation Report | Current | Thursday 04/27/06 at 09:29 |
Map Report | Current | Wednesday 10/11/06 at 23:48 |
Pad Report | Current | Wednesday 10/11/06 at 23:48 |
Place and Route Report | Current | Wednesday 10/11/06 at 23:48 |
Post Place and Route Static Timing Report | Current | Wednesday 10/11/06 at 23:48 |
Bitgen Report | Current | Wednesday 10/11/06 at 23:48 |