fre Project Status | |||
Project File: | fre.ise | Current State: | Translated |
Module Name: | fre |
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Target Device: | xc3s400-4pq208 |
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Product Version: | ISE 10.1.03 - Foundation Simulator |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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fre Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 15 | 3584 | 0% | |
Number of Slice Flip Flops | 27 | 7168 | 0% | |
Number of 4 input LUTs | 26 | 7168 | 0% | |
Number of bonded IOBs | 10 | 141 | 7% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 水 10 11 11:13:00 2006 | ||||
Translation Report | Current | 水 10 11 11:13:04 2006 | ||||
Map Report | ||||||
Place and Route Report | Current | 水 10 11 11:13:08 2006 | ||||
Static Timing Report | Current | 水 10 11 11:13:10 2006 | ||||
Bitgen Report | Current | 水 10 11 11:13:16 2006 |