Design Overview for flash_wr

PropertyValue
Project Name:d:\xilinx\myproject\xilinxsamples_v2.0\3s400changed\part_three\s17_flash\project
Target Device:xc3s400
Report Generated:Friday 10/19/07 at 10:43
Printable Summary (View as HTML)flash_wr_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:857,1681% 
Number of 4 input LUTs:1877,1682% 
Logic Distribution:    
Number of occupied Slices:1173,5843% 
Number of Slices containing only related logic:117117100% 
Number of Slices containing unrelated logic:01170% 
Total Number 4 input LUTs:1967,1682% 
Number used as logic:187   
Number used as a route-thru:9   
Number of bonded IOBs:3614125% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentFriday 10/19/07 at 10:42
Translation ReportCurrentFriday 10/19/07 at 10:42
Map ReportCurrentFriday 10/19/07 at 10:42
Pad ReportCurrentFriday 10/19/07 at 10:43
Place and Route ReportCurrentFriday 10/19/07 at 10:43
Post Place and Route Static Timing ReportCurrentFriday 10/19/07 at 10:43
Bitgen ReportCurrentFriday 10/19/07 at 10:43