Property | Value |
Project Name: | d:\xilinx\myproject\xilinxsamples_v2.0\3s400changed\part_three\s16_sdram\part2\project |
Target Device: | xc3s400 |
Report Generated: | Friday 10/19/07 at 10:45 |
Printable Summary (View as HTML) | test_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 41 | 7,168 | 1% | |
Number of 4 input LUTs: | 68 | 7,168 | 1% | |
Logic Distribution: | ||||
Number of occupied Slices: | 59 | 3,584 | 1% | |
Number of Slices containing only related logic: | 59 | 59 | 100% | |
Number of Slices containing unrelated logic: | 0 | 59 | 0% | |
Total Number of 4 input LUTs: | 68 | 7,168 | 1% | |
Number of bonded IOBs: | 66 | 141 | 46% | |
Number of GCLKs: | 1 | 8 | 12% |
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Friday 10/19/07 at 10:44 |
Translation Report | Current | Friday 10/19/07 at 10:45 |
Map Report | Current | Friday 10/19/07 at 10:45 |
Pad Report | Current | Friday 10/19/07 at 10:45 |
Place and Route Report | Current | Friday 10/19/07 at 10:45 |
Post Place and Route Static Timing Report | Current | Friday 10/19/07 at 10:45 |
Bitgen Report | Current | Friday 10/19/07 at 10:45 |