Design Overview for top

PropertyValue
Project Name:d:\xilinx\myproject\xilinxsamples_v2.0\3s400changed\part_one\s6_unjounce\project
Target Device:xc3s400
Report Generated:Tuesday 10/09/07 at 11:03
Printable Summary (View as HTML)top_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:377,1681% 
Number of 4 input LUTs:217,1681% 
Logic Distribution:    
Number of occupied Slices:233,5841% 
Number of Slices containing only related logic:2323100% 
Number of Slices containing unrelated logic:0230% 
Total Number 4 input LUTs:437,1681% 
Number used as logic:21   
Number used as a route-thru:22   
Number of bonded IOBs:1514110% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentTuesday 10/09/07 at 11:02
Translation ReportCurrentTuesday 10/09/07 at 11:02
Map ReportCurrentTuesday 10/09/07 at 11:02
Pad ReportCurrentTuesday 10/09/07 at 11:02
Place and Route ReportCurrentTuesday 10/09/07 at 11:02
Post Place and Route Static Timing ReportCurrentTuesday 10/09/07 at 11:02
Bitgen ReportCurrentTuesday 10/09/07 at 11:03