; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --debug -c --asm --interleave -o..\OBJ\system_stm32f10x.o --asm_dir=..\LIST\ --list_dir=..\LIST\ --depend=..\OBJ\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\CMSIS\CM3\CoreSupport -I..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\..\USER\INC -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=..\OBJ\system_stm32f10x.crf ..\..\USER\SRC\system_stm32f10x.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SetSysClockTo72 PROC
;;;986      */
;;;987    static void SetSysClockTo72(void)
000000  b50c              PUSH     {r2,r3,lr}
;;;988    {
;;;989      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002  2000              MOVS     r0,#0
000004  9001              STR      r0,[sp,#4]
000006  9000              STR      r0,[sp,#0]
;;;990      
;;;991      /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
;;;992      /* Enable HSE */    
;;;993      RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000008  486b              LDR      r0,|L1.440|
00000a  6800              LDR      r0,[r0,#0]
00000c  f4403080          ORR      r0,r0,#0x10000
000010  4969              LDR      r1,|L1.440|
000012  6008              STR      r0,[r1,#0]
;;;994     
;;;995      /* Wait till HSE is ready and if Time out is reached exit */
;;;996      do
000014  bf00              NOP      
                  |L1.22|
;;;997      {
;;;998        HSEStatus = RCC->CR & RCC_CR_HSERDY;
000016  4868              LDR      r0,|L1.440|
000018  6800              LDR      r0,[r0,#0]
00001a  f4003000          AND      r0,r0,#0x20000
00001e  9000              STR      r0,[sp,#0]
;;;999        StartUpCounter++;  
000020  9801              LDR      r0,[sp,#4]
000022  1c40              ADDS     r0,r0,#1
000024  9001              STR      r0,[sp,#4]
;;;1000     } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
000026  9800              LDR      r0,[sp,#0]
000028  b918              CBNZ     r0,|L1.50|
00002a  9801              LDR      r0,[sp,#4]
00002c  f5b06fa0          CMP      r0,#0x500
000030  d1f1              BNE      |L1.22|
                  |L1.50|
;;;1001   
;;;1002     if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000032  4861              LDR      r0,|L1.440|
000034  6800              LDR      r0,[r0,#0]
000036  f4103f00          TST      r0,#0x20000
00003a  d002              BEQ      |L1.66|
;;;1003     {
;;;1004       HSEStatus = (uint32_t)0x01;
00003c  2001              MOVS     r0,#1
00003e  9000              STR      r0,[sp,#0]
000040  e001              B        |L1.70|
                  |L1.66|
;;;1005     }
;;;1006     else
;;;1007     {
;;;1008       HSEStatus = (uint32_t)0x00;
000042  2000              MOVS     r0,#0
000044  9000              STR      r0,[sp,#0]
                  |L1.70|
;;;1009     }  
;;;1010   
;;;1011     if (HSEStatus == (uint32_t)0x01)
000046  9800              LDR      r0,[sp,#0]
000048  2801              CMP      r0,#1
00004a  d142              BNE      |L1.210|
;;;1012     {
;;;1013       /* Enable Prefetch Buffer */
;;;1014       FLASH->ACR |= FLASH_ACR_PRFTBE;
00004c  485b              LDR      r0,|L1.444|
00004e  6800              LDR      r0,[r0,#0]
000050  f0400010          ORR      r0,r0,#0x10
000054  4959              LDR      r1,|L1.444|
000056  6008              STR      r0,[r1,#0]
;;;1015   
;;;1016       /* Flash 2 wait state */
;;;1017       FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
000058  4608              MOV      r0,r1
00005a  6800              LDR      r0,[r0,#0]
00005c  f0200003          BIC      r0,r0,#3
000060  6008              STR      r0,[r1,#0]
;;;1018       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
000062  4608              MOV      r0,r1
000064  6800              LDR      r0,[r0,#0]
000066  f0400002          ORR      r0,r0,#2
00006a  6008              STR      r0,[r1,#0]
;;;1019   
;;;1020    
;;;1021       /* HCLK = SYSCLK */
;;;1022       RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00006c  4852              LDR      r0,|L1.440|
00006e  6840              LDR      r0,[r0,#4]
000070  4951              LDR      r1,|L1.440|
000072  6048              STR      r0,[r1,#4]
;;;1023         
;;;1024       /* PCLK2 = HCLK */
;;;1025       RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
000074  4608              MOV      r0,r1
000076  6840              LDR      r0,[r0,#4]
000078  6048              STR      r0,[r1,#4]
;;;1026       
;;;1027       /* PCLK1 = HCLK */
;;;1028       RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00007a  4608              MOV      r0,r1
00007c  6840              LDR      r0,[r0,#4]
00007e  f4406080          ORR      r0,r0,#0x400
000082  6048              STR      r0,[r1,#4]
;;;1029   
;;;1030   #ifdef STM32F10X_CL
;;;1031       /* Configure PLLs ------------------------------------------------------*/
;;;1032       /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
;;;1033       /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
;;;1034           
;;;1035       RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
;;;1036                                 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
;;;1037       RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
;;;1038                                RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
;;;1039     
;;;1040       /* Enable PLL2 */
;;;1041       RCC->CR |= RCC_CR_PLL2ON;
;;;1042       /* Wait till PLL2 is ready */
;;;1043       while((RCC->CR & RCC_CR_PLL2RDY) == 0)
;;;1044       {
;;;1045       }
;;;1046       
;;;1047      
;;;1048       /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
;;;1049       RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
;;;1050       RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
;;;1051                               RCC_CFGR_PLLMULL9); 
;;;1052   #else    
;;;1053       /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
;;;1054       RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
000084  4608              MOV      r0,r1
000086  6840              LDR      r0,[r0,#4]
000088  f420107c          BIC      r0,r0,#0x3f0000
00008c  6048              STR      r0,[r1,#4]
;;;1055                                           RCC_CFGR_PLLMULL));
;;;1056       RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
00008e  4608              MOV      r0,r1
000090  6840              LDR      r0,[r0,#4]
000092  f44010e8          ORR      r0,r0,#0x1d0000
000096  6048              STR      r0,[r1,#4]
;;;1057   #endif /* STM32F10X_CL */
;;;1058   
;;;1059       /* Enable PLL */
;;;1060       RCC->CR |= RCC_CR_PLLON;
000098  4608              MOV      r0,r1
00009a  6800              LDR      r0,[r0,#0]
00009c  f0407080          ORR      r0,r0,#0x1000000
0000a0  6008              STR      r0,[r1,#0]
;;;1061   
;;;1062       /* Wait till PLL is ready */
;;;1063       while((RCC->CR & RCC_CR_PLLRDY) == 0)
0000a2  bf00              NOP      
                  |L1.164|
0000a4  4844              LDR      r0,|L1.440|
0000a6  6800              LDR      r0,[r0,#0]
0000a8  f0107f00          TST      r0,#0x2000000
0000ac  d0fa              BEQ      |L1.164|
;;;1064       {
;;;1065       }
;;;1066       
;;;1067       /* Select PLL as system clock source */
;;;1068       RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0000ae  4842              LDR      r0,|L1.440|
0000b0  6840              LDR      r0,[r0,#4]
0000b2  f0200003          BIC      r0,r0,#3
0000b6  4940              LDR      r1,|L1.440|
0000b8  6048              STR      r0,[r1,#4]
;;;1069       RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
0000ba  4608              MOV      r0,r1
0000bc  6840              LDR      r0,[r0,#4]
0000be  f0400002          ORR      r0,r0,#2
0000c2  6048              STR      r0,[r1,#4]
;;;1070   
;;;1071       /* Wait till PLL is used as system clock source */
;;;1072       while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0000c4  bf00              NOP      
                  |L1.198|
0000c6  483c              LDR      r0,|L1.440|
0000c8  6840              LDR      r0,[r0,#4]
0000ca  f000000c          AND      r0,r0,#0xc
0000ce  2808              CMP      r0,#8
0000d0  d1f9              BNE      |L1.198|
                  |L1.210|
;;;1073       {
;;;1074       }
;;;1075     }
;;;1076     else
;;;1077     { /* If HSE fails to start-up, the application will have wrong clock 
;;;1078            configuration. User can add here some code to deal with this error */
;;;1079     }
;;;1080   }
0000d2  bd0c              POP      {r2,r3,pc}
;;;1081   #endif
                          ENDP

                  SetSysClock PROC
;;;418      */
;;;419    static void SetSysClock(void)
0000d4  b510              PUSH     {r4,lr}
;;;420    {
;;;421    #ifdef SYSCLK_FREQ_HSE
;;;422      SetSysClockToHSE();
;;;423    #elif defined SYSCLK_FREQ_24MHz
;;;424      SetSysClockTo24();
;;;425    #elif defined SYSCLK_FREQ_36MHz
;;;426      SetSysClockTo36();
;;;427    #elif defined SYSCLK_FREQ_48MHz
;;;428      SetSysClockTo48();
;;;429    #elif defined SYSCLK_FREQ_56MHz
;;;430      SetSysClockTo56();  
;;;431    #elif defined SYSCLK_FREQ_72MHz
;;;432      SetSysClockTo72();
0000d6  f7fffffe          BL       SetSysClockTo72
;;;433    #endif
;;;434     
;;;435     /* If none of the define above is enabled, the HSI is used as System clock
;;;436        source (default after reset) */ 
;;;437    }
0000da  bd10              POP      {r4,pc}
;;;438    
                          ENDP

                  SystemInit PROC
;;;211      */
;;;212    void SystemInit (void)
0000dc  b510              PUSH     {r4,lr}
;;;213    {
;;;214      /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
;;;215      /* Set HSION bit */
;;;216      RCC->CR |= (uint32_t)0x00000001;
0000de  4836              LDR      r0,|L1.440|
0000e0  6800              LDR      r0,[r0,#0]
0000e2  f0400001          ORR      r0,r0,#1
0000e6  4934              LDR      r1,|L1.440|
0000e8  6008              STR      r0,[r1,#0]
;;;217    
;;;218      /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;219    #ifndef STM32F10X_CL
;;;220      RCC->CFGR &= (uint32_t)0xF8FF0000;
0000ea  4608              MOV      r0,r1
0000ec  6840              LDR      r0,[r0,#4]
0000ee  4934              LDR      r1,|L1.448|
0000f0  4008              ANDS     r0,r0,r1
0000f2  4931              LDR      r1,|L1.440|
0000f4  6048              STR      r0,[r1,#4]
;;;221    #else
;;;222      RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;223    #endif /* STM32F10X_CL */   
;;;224      
;;;225      /* Reset HSEON, CSSON and PLLON bits */
;;;226      RCC->CR &= (uint32_t)0xFEF6FFFF;
0000f6  4608              MOV      r0,r1
0000f8  6800              LDR      r0,[r0,#0]
0000fa  4932              LDR      r1,|L1.452|
0000fc  4008              ANDS     r0,r0,r1
0000fe  492e              LDR      r1,|L1.440|
000100  6008              STR      r0,[r1,#0]
;;;227    
;;;228      /* Reset HSEBYP bit */
;;;229      RCC->CR &= (uint32_t)0xFFFBFFFF;
000102  4608              MOV      r0,r1
000104  6800              LDR      r0,[r0,#0]
000106  f4202080          BIC      r0,r0,#0x40000
00010a  6008              STR      r0,[r1,#0]
;;;230    
;;;231      /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;232      RCC->CFGR &= (uint32_t)0xFF80FFFF;
00010c  4608              MOV      r0,r1
00010e  6840              LDR      r0,[r0,#4]
000110  f42000fe          BIC      r0,r0,#0x7f0000
000114  6048              STR      r0,[r1,#4]
;;;233    
;;;234    #ifdef STM32F10X_CL
;;;235      /* Reset PLL2ON and PLL3ON bits */
;;;236      RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;237    
;;;238      /* Disable all interrupts and clear pending bits  */
;;;239      RCC->CIR = 0x00FF0000;
;;;240    
;;;241      /* Reset CFGR2 register */
;;;242      RCC->CFGR2 = 0x00000000;
;;;243    #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;244      /* Disable all interrupts and clear pending bits  */
;;;245      RCC->CIR = 0x009F0000;
;;;246    
;;;247      /* Reset CFGR2 register */
;;;248      RCC->CFGR2 = 0x00000000;      
;;;249    #else
;;;250      /* Disable all interrupts and clear pending bits  */
;;;251      RCC->CIR = 0x009F0000;
000116  f44f001f          MOV      r0,#0x9f0000
00011a  6088              STR      r0,[r1,#8]
;;;252    #endif /* STM32F10X_CL */
;;;253        
;;;254    #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
;;;255      #ifdef DATA_IN_ExtSRAM
;;;256        SystemInit_ExtMemCtl(); 
;;;257      #endif /* DATA_IN_ExtSRAM */
;;;258    #endif 
;;;259    
;;;260      /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
;;;261      /* Configure the Flash Latency cycles and enable prefetch buffer */
;;;262      SetSysClock();
00011c  f7fffffe          BL       SetSysClock
;;;263    
;;;264    #ifdef VECT_TAB_SRAM
;;;265      SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
;;;266    #else
;;;267      SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
000120  f04f6000          MOV      r0,#0x8000000
000124  4928              LDR      r1,|L1.456|
000126  6008              STR      r0,[r1,#0]
;;;268    #endif 
;;;269    }
000128  bd10              POP      {r4,pc}
;;;270    
                          ENDP

                  SystemCoreClockUpdate PROC
;;;305      */
;;;306    void SystemCoreClockUpdate (void)
00012a  b510              PUSH     {r4,lr}
;;;307    {
;;;308      uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00012c  2100              MOVS     r1,#0
00012e  2000              MOVS     r0,#0
000130  2200              MOVS     r2,#0
;;;309    
;;;310    #ifdef  STM32F10X_CL
;;;311      uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
;;;312    #endif /* STM32F10X_CL */
;;;313    
;;;314    #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;315      uint32_t prediv1factor = 0;
;;;316    #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
;;;317        
;;;318      /* Get SYSCLK source -------------------------------------------------------*/
;;;319      tmp = RCC->CFGR & RCC_CFGR_SWS;
000132  4b21              LDR      r3,|L1.440|
000134  685b              LDR      r3,[r3,#4]
000136  f003010c          AND      r1,r3,#0xc
;;;320      
;;;321      switch (tmp)
00013a  b121              CBZ      r1,|L1.326|
00013c  2904              CMP      r1,#4
00013e  d006              BEQ      |L1.334|
000140  2908              CMP      r1,#8
000142  d128              BNE      |L1.406|
000144  e007              B        |L1.342|
                  |L1.326|
;;;322      {
;;;323        case 0x00:  /* HSI used as system clock */
;;;324          SystemCoreClock = HSI_VALUE;
000146  4b21              LDR      r3,|L1.460|
000148  4c21              LDR      r4,|L1.464|
00014a  6023              STR      r3,[r4,#0]  ; SystemCoreClock
;;;325          break;
00014c  e027              B        |L1.414|
                  |L1.334|
;;;326        case 0x04:  /* HSE used as system clock */
;;;327          SystemCoreClock = HSE_VALUE;
00014e  4b1f              LDR      r3,|L1.460|
000150  4c1f              LDR      r4,|L1.464|
000152  6023              STR      r3,[r4,#0]  ; SystemCoreClock
;;;328          break;
000154  e023              B        |L1.414|
                  |L1.342|
;;;329        case 0x08:  /* PLL used as system clock */
;;;330    
;;;331          /* Get PLL clock source and multiplication factor ----------------------*/
;;;332          pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
000156  4b18              LDR      r3,|L1.440|
000158  685b              LDR      r3,[r3,#4]
00015a  f4031070          AND      r0,r3,#0x3c0000
;;;333          pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00015e  4b16              LDR      r3,|L1.440|
000160  685b              LDR      r3,[r3,#4]
000162  f4033280          AND      r2,r3,#0x10000
;;;334          
;;;335    #ifndef STM32F10X_CL      
;;;336          pllmull = ( pllmull >> 18) + 2;
000166  2302              MOVS     r3,#2
000168  eb034090          ADD      r0,r3,r0,LSR #18
;;;337          
;;;338          if (pllsource == 0x00)
00016c  b922              CBNZ     r2,|L1.376|
;;;339          {
;;;340            /* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;341            SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00016e  4b19              LDR      r3,|L1.468|
000170  4343              MULS     r3,r0,r3
000172  4c17              LDR      r4,|L1.464|
000174  6023              STR      r3,[r4,#0]  ; SystemCoreClock
000176  e00d              B        |L1.404|
                  |L1.376|
;;;342          }
;;;343          else
;;;344          {
;;;345     #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;346           prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
;;;347           /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;348           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
;;;349     #else
;;;350            /* HSE selected as PLL clock entry */
;;;351            if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
000178  4b0f              LDR      r3,|L1.440|
00017a  685b              LDR      r3,[r3,#4]
00017c  f4133f00          TST      r3,#0x20000
000180  d004              BEQ      |L1.396|
;;;352            {/* HSE oscillator clock divided by 2 */
;;;353              SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
000182  4b14              LDR      r3,|L1.468|
000184  4343              MULS     r3,r0,r3
000186  4c12              LDR      r4,|L1.464|
000188  6023              STR      r3,[r4,#0]  ; SystemCoreClock
00018a  e003              B        |L1.404|
                  |L1.396|
;;;354            }
;;;355            else
;;;356            {
;;;357              SystemCoreClock = HSE_VALUE * pllmull;
00018c  4b0f              LDR      r3,|L1.460|
00018e  4343              MULS     r3,r0,r3
000190  4c0f              LDR      r4,|L1.464|
000192  6023              STR      r3,[r4,#0]  ; SystemCoreClock
                  |L1.404|
;;;358            }
;;;359     #endif
;;;360          }
;;;361    #else
;;;362          pllmull = pllmull >> 18;
;;;363          
;;;364          if (pllmull != 0x0D)
;;;365          {
;;;366             pllmull += 2;
;;;367          }
;;;368          else
;;;369          { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;370            pllmull = 13 / 2; 
;;;371          }
;;;372                
;;;373          if (pllsource == 0x00)
;;;374          {
;;;375            /* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;376            SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
;;;377          }
;;;378          else
;;;379          {/* PREDIV1 selected as PLL clock entry */
;;;380            
;;;381            /* Get PREDIV1 clock source and division factor */
;;;382            prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
;;;383            prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
;;;384            
;;;385            if (prediv1source == 0)
;;;386            { 
;;;387              /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;388              SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
;;;389            }
;;;390            else
;;;391            {/* PLL2 clock selected as PREDIV1 clock entry */
;;;392              
;;;393              /* Get PREDIV2 division factor and PLL2 multiplication factor */
;;;394              prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
;;;395              pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
;;;396              SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
;;;397            }
;;;398          }
;;;399    #endif /* STM32F10X_CL */ 
;;;400          break;
000194  e003              B        |L1.414|
                  |L1.406|
;;;401    
;;;402        default:
;;;403          SystemCoreClock = HSI_VALUE;
000196  4b0d              LDR      r3,|L1.460|
000198  4c0d              LDR      r4,|L1.464|
00019a  6023              STR      r3,[r4,#0]  ; SystemCoreClock
;;;404          break;
00019c  bf00              NOP      
                  |L1.414|
00019e  bf00              NOP                            ;325
;;;405      }
;;;406      
;;;407      /* Compute HCLK clock frequency ----------------*/
;;;408      /* Get HCLK prescaler */
;;;409      tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
0001a0  4b05              LDR      r3,|L1.440|
0001a2  685b              LDR      r3,[r3,#4]
0001a4  f3c31303          UBFX     r3,r3,#4,#4
0001a8  4c0b              LDR      r4,|L1.472|
0001aa  5ce1              LDRB     r1,[r4,r3]
;;;410      /* HCLK clock frequency */
;;;411      SystemCoreClock >>= tmp;  
0001ac  4b08              LDR      r3,|L1.464|
0001ae  681b              LDR      r3,[r3,#0]  ; SystemCoreClock
0001b0  40cb              LSRS     r3,r3,r1
0001b2  4c07              LDR      r4,|L1.464|
0001b4  6023              STR      r3,[r4,#0]  ; SystemCoreClock
;;;412    }
0001b6  bd10              POP      {r4,pc}
;;;413    
                          ENDP

                  |L1.440|
                          DCD      0x40021000
                  |L1.444|
                          DCD      0x40022000
                  |L1.448|
                          DCD      0xf8ff0000
                  |L1.452|
                          DCD      0xfef6ffff
                  |L1.456|
                          DCD      0xe000ed08
                  |L1.460|
                          DCD      0x007a1200
                  |L1.464|
                          DCD      SystemCoreClock
                  |L1.468|
                          DCD      0x003d0900
                  |L1.472|
                          DCD      AHBPrescTable

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x044aa200
                  AHBPrescTable
000004  00000000          DCB      0x00,0x00,0x00,0x00
000008  00000000          DCB      0x00,0x00,0x00,0x00
00000c  01020304          DCB      0x01,0x02,0x03,0x04
000010  06070809          DCB      0x06,0x07,0x08,0x09
