; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --debug -c --asm --interleave -o..\OBJ\stm32f10x_it.o --asm_dir=..\LIST\ --list_dir=..\LIST\ --depend=..\OBJ\stm32f10x_it.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\CMSIS\CM3\CoreSupport -I..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\..\USER\INC -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=..\OBJ\stm32f10x_it.crf ..\..\USER\SRC\stm32f10x_it.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  NMI_Handler PROC
;;;45     *******************************************************************************/
;;;46     void NMI_Handler(void)
000000  4770              BX       lr
;;;47     {
;;;48     }
;;;49     
                          ENDP

                  HardFault_Handler PROC
;;;56     *******************************************************************************/
;;;57     void HardFault_Handler(void)
000002  bf00              NOP      
                  |L1.4|
;;;58     {
;;;59       /* Go to infinite loop when Hard Fault exception occurs */
;;;60       while (1)
000004  e7fe              B        |L1.4|
;;;61       {
;;;62       }
;;;63     }
;;;64     
                          ENDP

                  MemManage_Handler PROC
;;;71     *******************************************************************************/
;;;72     void MemManage_Handler(void)
000006  bf00              NOP      
                  |L1.8|
;;;73     {
;;;74       /* Go to infinite loop when Memory Manage exception occurs */
;;;75       while (1)
000008  e7fe              B        |L1.8|
;;;76       {
;;;77       }
;;;78     }
;;;79     
                          ENDP

                  BusFault_Handler PROC
;;;86     *******************************************************************************/
;;;87     void BusFault_Handler(void)
00000a  bf00              NOP      
                  |L1.12|
;;;88     {
;;;89       /* Go to infinite loop when Bus Fault exception occurs */
;;;90       while (1)
00000c  e7fe              B        |L1.12|
;;;91       {
;;;92       }
;;;93     }
;;;94     
                          ENDP

                  UsageFault_Handler PROC
;;;101    *******************************************************************************/
;;;102    void UsageFault_Handler(void)
00000e  bf00              NOP      
                  |L1.16|
;;;103    {
;;;104      /* Go to infinite loop when Usage Fault exception occurs */
;;;105      while (1)
000010  e7fe              B        |L1.16|
;;;106      {
;;;107      }
;;;108    }
;;;109    
                          ENDP

                  SVC_Handler PROC
;;;116    *******************************************************************************/
;;;117    void SVC_Handler(void)
000012  4770              BX       lr
;;;118    {
;;;119    }
;;;120    
                          ENDP

                  DebugMon_Handler PROC
;;;127    *******************************************************************************/
;;;128    void DebugMon_Handler(void)
000014  4770              BX       lr
;;;129    {
;;;130    }
;;;131    
                          ENDP

                  PendSV_Handler PROC
;;;138    *******************************************************************************/
;;;139    void PendSV_Handler(void)
000016  4770              BX       lr
;;;140    {
;;;141    }
;;;142    
                          ENDP

                  SysTick_Handler PROC
;;;149    *******************************************************************************/
;;;150    void SysTick_Handler(void)
000018  4770              BX       lr
;;;151    {
;;;152    }
;;;153    
                          ENDP

                  USB_HP_CAN1_TX_IRQHandler PROC
;;;166    *******************************************************************************/
;;;167    void USB_HP_CAN1_TX_IRQHandler(void)
00001a  4770              BX       lr
;;;168    {
;;;169      //CTR_HP();
;;;170    }
;;;171    
                          ENDP

                  USB_LP_CAN1_RX0_IRQHandler PROC
;;;179    *******************************************************************************/
;;;180    void USB_LP_CAN1_RX0_IRQHandler(void)
00001c  4770              BX       lr
;;;181    {
;;;182      //USB_Istr();
;;;183    }
;;;184    #endif /* STM32F10X_CL */
                          ENDP

                  SDIO_IRQHandler PROC
;;;194    *******************************************************************************/
;;;195    void SDIO_IRQHandler(void)
00001e  4770              BX       lr
;;;196    { 
;;;197      /* Process All SDIO Interrupt Sources */
;;;198      //SD_ProcessIRQSrc();
;;;199      
;;;200    }
;;;201    #endif /* STM32F10X_HD | STM32F10X_XL*/
                          ENDP

                  USART1_IRQHandler PROC
;;;224    
;;;225    void USART_COM1_IRQHandler(void)
000020  b510              PUSH     {r4,lr}
;;;226    {
;;;227    	USART1_RxIntHandler();
000022  f7fffffe          BL       USART1_RxIntHandler
;;;228    }
000026  bd10              POP      {r4,pc}
;;;229    
                          ENDP

                  USART2_IRQHandler PROC
;;;230    void USART_COM2_IRQHandler(void)
000028  b510              PUSH     {r4,lr}
;;;231    {
;;;232      	USART2_RxIntHandler();
00002a  f7fffffe          BL       USART2_RxIntHandler
;;;233    }
00002e  bd10              POP      {r4,pc}
;;;234    
                          ENDP

                  EXTI4_IRQHandler PROC
;;;235    void EXTI4_IRQHandler(void)
000030  b510              PUSH     {r4,lr}
;;;236    { 
;;;237    	EXTI_ClearITPendingBit(EXTI_Line4);  		//EXTI4·λ     //жϱ־λ
000032  2010              MOVS     r0,#0x10
000034  f7fffffe          BL       EXTI_ClearITPendingBit
;;;238    	Vsync_Flag++;
000038  4861              LDR      r0,|L1.448|
00003a  7800              LDRB     r0,[r0,#0]  ; Vsync_Flag
00003c  1c40              ADDS     r0,r0,#1
00003e  4960              LDR      r1,|L1.448|
000040  7008              STRB     r0,[r1,#0]
;;;239    	if(Vsync_Flag==1)    //FIFOдָ븴λ
000042  4608              MOV      r0,r1
000044  7800              LDRB     r0,[r0,#0]  ; Vsync_Flag
000046  2801              CMP      r0,#1
000048  d118              BNE      |L1.124|
;;;240    	{
;;;241    	    FIFO_WRST=1;
00004a  495e              LDR      r1,|L1.452|
00004c  6008              STR      r0,[r1,#0]
;;;242    		FIFO_WRST=0;
00004e  f04f0000          MOV      r0,#0
000052  495d              LDR      r1,|L1.456|
000054  f8c10194          STR      r0,[r1,#0x194]
;;;243     		for(i=0;i<100;i++);
000058  495c              LDR      r1,|L1.460|
00005a  8008              STRH     r0,[r1,#0]
00005c  e004              B        |L1.104|
                  |L1.94|
00005e  485b              LDR      r0,|L1.460|
000060  8800              LDRH     r0,[r0,#0]  ; i
000062  1c40              ADDS     r0,r0,#1
000064  4959              LDR      r1,|L1.460|
000066  8008              STRH     r0,[r1,#0]
                  |L1.104|
000068  4858              LDR      r0,|L1.460|
00006a  8800              LDRH     r0,[r0,#0]  ; i
00006c  2864              CMP      r0,#0x64
00006e  dbf6              BLT      |L1.94|
;;;244    		FIFO_WRST=1;      
000070  2001              MOVS     r0,#1
000072  4954              LDR      r1,|L1.452|
000074  6008              STR      r0,[r1,#0]
;;;245    		FIFO_WR=1;	   //CMOSдFIFO
000076  4954              LDR      r1,|L1.456|
000078  f8c10184          STR      r0,[r1,#0x184]
                  |L1.124|
;;;246    		
;;;247    	}
;;;248    	if(Vsync_Flag==2)
00007c  4850              LDR      r0,|L1.448|
00007e  7800              LDRB     r0,[r0,#0]  ; Vsync_Flag
000080  2802              CMP      r0,#2
000082  d17d              BNE      |L1.384|
;;;249    	{
;;;250    	 	FIFO_WR=0;     //ֹCMOSдFIFO
000084  2000              MOVS     r0,#0
000086  4952              LDR      r1,|L1.464|
000088  6008              STR      r0,[r1,#0]
;;;251    		EXTI->IMR&=~(1<<4);	 //ֹⲿжϣ׼FIFOȡ
00008a  4852              LDR      r0,|L1.468|
00008c  6800              LDR      r0,[r0,#0]
00008e  f0200010          BIC      r0,r0,#0x10
000092  4950              LDR      r1,|L1.468|
000094  6008              STR      r0,[r1,#0]
;;;252    		EXTI->EMR&=~(1<<4);
000096  f1010004          ADD      r0,r1,#4
00009a  6800              LDR      r0,[r0,#0]
00009c  f0200010          BIC      r0,r0,#0x10
0000a0  f1010104          ADD      r1,r1,#4
0000a4  6008              STR      r0,[r1,#0]
;;;253    
;;;254    		FIFO_RRST=0;  //FIFOָ븴λ 
0000a6  f04f0000          MOV      r0,#0
0000aa  4947              LDR      r1,|L1.456|
0000ac  f8c1019c          STR      r0,[r1,#0x19c]
;;;255    		FIFO_RCK=0;                
0000b0  4949              LDR      r1,|L1.472|
0000b2  6008              STR      r0,[r1,#0]
;;;256    		FIFO_RCK=1;	
0000b4  f04f0001          MOV      r0,#1
0000b8  6008              STR      r0,[r1,#0]
;;;257    		FIFO_RCK=0;
0000ba  f04f0000          MOV      r0,#0
0000be  6008              STR      r0,[r1,#0]
;;;258    		FIFO_RCK=1;
0000c0  f04f0001          MOV      r0,#1
0000c4  6008              STR      r0,[r1,#0]
;;;259    	  	FIFO_RRST=1;
0000c6  4945              LDR      r1,|L1.476|
0000c8  6008              STR      r0,[r1,#0]
;;;260    
;;;261    		VC245_FIFO=1;	 //MCUTFT
0000ca  4945              LDR      r1,|L1.480|
0000cc  6008              STR      r0,[r1,#0]
;;;262    		VC245_7670=1;
0000ce  4945              LDR      r1,|L1.484|
0000d0  6008              STR      r0,[r1,#0]
;;;263    		WriteControl=1;	 
0000d2  4945              LDR      r1,|L1.488|
0000d4  6008              STR      r0,[r1,#0]
;;;264    		LCD_CS=0; 
0000d6  f04f0000          MOV      r0,#0
0000da  4944              LDR      r1,|L1.492|
0000dc  6008              STR      r0,[r1,#0]
;;;265    		Address_set(0,0,320-1,240-1); 
0000de  f04f03ef          MOV      r3,#0xef
0000e2  f240123f          MOV      r2,#0x13f
0000e6  4601              MOV      r1,r0
0000e8  4608              MOV      r0,r1
0000ea  f7fffffe          BL       Address_set
;;;266    
;;;267    		FIFO_OE=0;			  //FIFO  		
0000ee  2000              MOVS     r0,#0
0000f0  493f              LDR      r1,|L1.496|
0000f2  6008              STR      r0,[r1,#0]
;;;268    		VC245_FIFO=0;	 //FIFOֱTFT
0000f4  493a              LDR      r1,|L1.480|
0000f6  6008              STR      r0,[r1,#0]
;;;269    		VC245_7670=1;
0000f8  f04f0001          MOV      r0,#1
0000fc  4939              LDR      r1,|L1.484|
0000fe  6008              STR      r0,[r1,#0]
;;;270    		WriteControl=1;	 			  
000100  4939              LDR      r1,|L1.488|
000102  6008              STR      r0,[r1,#0]
;;;271    
;;;272    		LCD_RS=1;
000104  493b              LDR      r1,|L1.500|
000106  6008              STR      r0,[r1,#0]
;;;273    		LCD_RD=1;
000108  493b              LDR      r1,|L1.504|
00010a  6008              STR      r0,[r1,#0]
;;;274    		LCD_WR=0;
00010c  f04f0000          MOV      r0,#0
000110  f1010104          ADD      r1,r1,#4
000114  6008              STR      r0,[r1,#0]
;;;275    		for(i = 0; i < 9600; i ++)	 //ÿ׵TFT2.8ʾߴ320*240
000116  492d              LDR      r1,|L1.460|
000118  8008              STRH     r0,[r1,#0]
00011a  e033              B        |L1.388|
                  |L1.284|
;;;276    		 {	
;;;277    		 	for(j = 0; j < 8; j ++)
00011c  2000              MOVS     r0,#0
00011e  4937              LDR      r1,|L1.508|
000120  8008              STRH     r0,[r1,#0]
000122  e024              B        |L1.366|
                  |L1.292|
;;;278    			{										
;;;279    				FIFO_RCK=0;							
000124  2000              MOVS     r0,#0
000126  492c              LDR      r1,|L1.472|
000128  6008              STR      r0,[r1,#0]
;;;280    				FIFO_RCK=1;	
00012a  f04f0001          MOV      r0,#1
00012e  4926              LDR      r1,|L1.456|
000130  f8c10188          STR      r0,[r1,#0x188]
;;;281    				LCD_WR=0;	 				
000134  f04f0000          MOV      r0,#0
000138  4931              LDR      r1,|L1.512|
00013a  6008              STR      r0,[r1,#0]
;;;282    				LCD_WR=1;			
00013c  f04f0001          MOV      r0,#1
000140  6008              STR      r0,[r1,#0]
;;;283    				FIFO_RCK=0;						
000142  f04f0000          MOV      r0,#0
000146  4924              LDR      r1,|L1.472|
000148  6008              STR      r0,[r1,#0]
;;;284    				FIFO_RCK=1;		
00014a  f04f0001          MOV      r0,#1
00014e  6008              STR      r0,[r1,#0]
;;;285    				LCD_WR=0;				
000150  f04f0000          MOV      r0,#0
000154  492a              LDR      r1,|L1.512|
000156  6008              STR      r0,[r1,#0]
;;;286    				LCD_WR=1;			
000158  f04f0001          MOV      r0,#1
00015c  4929              LDR      r1,|L1.516|
00015e  f8c1019c          STR      r0,[r1,#0x19c]
000162  4826              LDR      r0,|L1.508|
000164  8800              LDRH     r0,[r0,#0]            ;277  ; j
000166  f1000001          ADD      r0,r0,#1              ;277
00016a  4924              LDR      r1,|L1.508|
00016c  8008              STRH     r0,[r1,#0]            ;277
                  |L1.366|
00016e  4823              LDR      r0,|L1.508|
000170  8800              LDRH     r0,[r0,#0]            ;277  ; j
000172  2808              CMP      r0,#8                 ;277
000174  dbd6              BLT      |L1.292|
000176  4815              LDR      r0,|L1.460|
000178  8800              LDRH     r0,[r0,#0]            ;275  ; i
00017a  1c40              ADDS     r0,r0,#1              ;275
00017c  4913              LDR      r1,|L1.460|
00017e  e000              B        |L1.386|
                  |L1.384|
000180  e01d              B        |L1.446|
                  |L1.386|
000182  8008              STRH     r0,[r1,#0]            ;275
                  |L1.388|
000184  4811              LDR      r0,|L1.460|
000186  8800              LDRH     r0,[r0,#0]            ;275  ; i
000188  f5b05f16          CMP      r0,#0x2580            ;275
00018c  dbc6              BLT      |L1.284|
;;;287    											   	
;;;288    			}
;;;289    		}
;;;290    		LCD_CS=1;
00018e  2001              MOVS     r0,#1
000190  4916              LDR      r1,|L1.492|
000192  6008              STR      r0,[r1,#0]
;;;291    		FIFO_OE=1;		 	  //ֹFIFO
000194  490c              LDR      r1,|L1.456|
000196  f8c10198          STR      r0,[r1,#0x198]
;;;292    		Vsync_Flag=0;	   
00019a  f04f0000          MOV      r0,#0
00019e  4908              LDR      r1,|L1.448|
0001a0  7008              STRB     r0,[r1,#0]
;;;293    		EXTI->IMR|=(1<<4);	  //ⲿжϣԱ֡ͼ
0001a2  480c              LDR      r0,|L1.468|
0001a4  6800              LDR      r0,[r0,#0]
0001a6  f0400010          ORR      r0,r0,#0x10
0001aa  490a              LDR      r1,|L1.468|
0001ac  6008              STR      r0,[r1,#0]
;;;294    		EXTI->EMR|=(1<<4);
0001ae  f1010004          ADD      r0,r1,#4
0001b2  6800              LDR      r0,[r0,#0]
0001b4  f0400010          ORR      r0,r0,#0x10
0001b8  f1010104          ADD      r1,r1,#4
0001bc  6008              STR      r0,[r1,#0]
                  |L1.446|
;;;295    	} 		
;;;296    		
;;;297    }
0001be  bd10              POP      {r4,pc}
;;;298    
                          ENDP

                  |L1.448|
                          DCD      Vsync_Flag
                  |L1.452|
                          DCD      0x42218194
                  |L1.456|
                          DCD      0x42218000
                  |L1.460|
                          DCD      i
                  |L1.464|
                          DCD      0x42218184
                  |L1.468|
                          DCD      0x40010400
                  |L1.472|
                          DCD      0x42218188
                  |L1.476|
                          DCD      0x4221819c
                  |L1.480|
                          DCD      0x42218180
                  |L1.484|
                          DCD      0x422201a8
                  |L1.488|
                          DCD      0x422201b4
                  |L1.492|
                          DCD      0x422201a4
                  |L1.496|
                          DCD      0x42218198
                  |L1.500|
                          DCD      0x422201a0
                  |L1.504|
                          DCD      0x42220198
                  |L1.508|
                          DCD      j
                  |L1.512|
                          DCD      0x4222019c
                  |L1.516|
                          DCD      0x42220000

                          AREA ||.data||, DATA, ALIGN=1

                  Vsync_Flag
000000  00                DCB      0x00
                  KEY
000001  00                DCB      0x00
                  i
000002  0000              DCB      0x00,0x00
                  j
000004  0000              DCB      0x00,0x00
                  ||t1||
000006  0000              DCB      0x00,0x00
                  ||t2||
000008  0000              DCB      0x00,0x00
