DEMO_A Project Status (09/09/2015 - 08:45:43)
Project File: DEMO_A.xise Parser Errors: No Errors
Module Name: DEMO_A Implementation State: Programming File Generated
Target Device: xc6slx9-2ftg256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
125 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 3 Failing Constraints
Environment: System Settings
  • Final Timing Score:
479942  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,256 11,440 10%  
    Number used as Flip Flops 1,256      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 1,487 5,720 25%  
    Number used as logic 1,437 5,720 25%  
        Number using O6 output only 833      
        Number using O5 output only 262      
        Number using O5 and O6 342      
        Number used as ROM 0      
    Number used as Memory 2 1,440 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 2      
            Number using O6 output only 2      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 48      
        Number with same-slice register load 29      
        Number with same-slice carry load 19      
        Number with other load 0      
Number of occupied Slices 502 1,430 35%  
Number of MUXCYs used 528 2,860 18%  
Number of LUT Flip Flop pairs used 1,656      
    Number with an unused Flip Flop 579 1,656 34%  
    Number with an unused LUT 169 1,656 10%  
    Number of fully used LUT-FF pairs 908 1,656 54%  
    Number of unique control sets 96      
    Number of slice register sites lost
        to control set restrictions
350 11,440 3%  
Number of bonded IOBs 91 186 48%  
    Number of LOCed IOBs 91 91 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 7 16 43%  
    Number used as BUFGs 7      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 1 200 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.85      
 
Performance Summary [-]
Final Timing Score: 479942 (Setup: 479942, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 3 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent周二 九月 8 21:45:37 20150116 Warnings (0 new)54 Infos (0 new)
Translation ReportCurrent周三 九月 9 08:44:45 2015004 Infos (0 new)
Map ReportCurrent周三 九月 9 08:45:06 201504 Warnings (0 new)10 Infos (0 new)
Place and Route ReportCurrent周三 九月 9 08:45:20 201504 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrent周三 九月 9 08:45:25 2015003 Infos (0 new)
Bitgen ReportCurrent周三 九月 9 08:45:35 201501 Warning (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent周三 九月 9 08:45:35 2015
WebTalk Log FileCurrent周三 九月 9 08:45:43 2015

Date Generated: 09/09/2015 -