sd_sdram_vga Project Status (07/11/2015 - 13:45:19)
Project File: DEMO_A.xise Parser Errors: No Errors
Module Name: sd_sdram_vga Implementation State: Programming File Not Generated
Target Device: xc6slx9-2ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 841 11,440 7%  
    Number used as Flip Flops 841      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 925 5,720 16%  
    Number used as logic 873 5,720 15%  
        Number using O6 output only 586      
        Number using O5 output only 81      
        Number using O5 and O6 206      
        Number used as ROM 0      
    Number used as Memory 2 1,440 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 2      
            Number using O6 output only 2      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 50      
        Number with same-slice register load 42      
        Number with same-slice carry load 8      
        Number with other load 0      
Number of occupied Slices 288 1,430 20%  
Number of MUXCYs used 320 2,860 11%  
Number of LUT Flip Flop pairs used 981      
    Number with an unused Flip Flop 249 981 25%  
    Number with an unused LUT 56 981 5%  
    Number of fully used LUT-FF pairs 676 981 68%  
    Number of unique control sets 55      
    Number of slice register sites lost
        to control set restrictions
213 11,440 1%  
Number of bonded IOBs 67 186 36%  
    Number of LOCed IOBs 67 67 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 5 16 31%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 1 200 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.20      
 
Performance Summary [-]
Final Timing Score: 488100 (Setup: 488100, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 3 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent周五 七月 10 13:55:21 2015   
Translation ReportCurrent周六 七月 11 10:05:00 2015   
Map ReportCurrent周六 七月 11 10:05:17 2015   
Place and Route ReportCurrent周六 七月 11 10:05:28 2015   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of Date周五 七月 10 13:55:59 2015   
Bitgen ReportCurrent周六 七月 11 10:05:36 2015   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent周六 七月 11 13:45:13 2015
WebTalk Log FileCurrent周六 七月 11 13:45:19 2015

Date Generated: 07/11/2015 -