Environment Settings | ||||
Environment Variable | xst | ngdbuild | map | par |
PATHEXT | < data not available > | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
Path | < data not available > | D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt; D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt; d:\ispLEVER_Classic1_7\ispcpld\bin; d:\ispLEVER_Classic1_7\ispFPGA\bin\nt; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib; D:\ispTOOLS8_1\ispcpld\bin; D:\ispTOOLS8_1\ispLeverDSP; D:\ispTOOLS8_1\ispFPGA\bin\nt; D:\ispTOOLS8_1\ispFPGA\data; D:\ispTOOLS8_1\active-hdl\bin; D:/Program Files/Texas Instruments/xdctools_3_16_02_32; D:\Program Files\ARM\ADSv1_2\bin; D:\Program Files\AMD APP\bin\x86; D:\WINDOWS\system32; D:\WINDOWS; D:\WINDOWS\System32\Wbem; D:\Program Files\Common Files\Thunder Network\KanKan\Codecs; D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt; D:\Program Files\Cadence\SPB_16.3\tools\bin; D:\Program Files\Cadence\SPB_16.3\tools\fet\bin; D:\Program Files\Cadence\SPB_16.3\tools\Capture; D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin; D:\altera\quartus60\bin; D:\altera\quartus60\win; D:\Program Files\ATI Technologies\ATI.ACE\Core-Static; d:\program files\Modeltech_6.1f\win32; D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib; D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib |
D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt; D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt; d:\ispLEVER_Classic1_7\ispcpld\bin; d:\ispLEVER_Classic1_7\ispFPGA\bin\nt; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib; D:\ispTOOLS8_1\ispcpld\bin; D:\ispTOOLS8_1\ispLeverDSP; D:\ispTOOLS8_1\ispFPGA\bin\nt; D:\ispTOOLS8_1\ispFPGA\data; D:\ispTOOLS8_1\active-hdl\bin; D:/Program Files/Texas Instruments/xdctools_3_16_02_32; D:\Program Files\ARM\ADSv1_2\bin; D:\Program Files\AMD APP\bin\x86; D:\WINDOWS\system32; D:\WINDOWS; D:\WINDOWS\System32\Wbem; D:\Program Files\Common Files\Thunder Network\KanKan\Codecs; D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt; D:\Program Files\Cadence\SPB_16.3\tools\bin; D:\Program Files\Cadence\SPB_16.3\tools\fet\bin; D:\Program Files\Cadence\SPB_16.3\tools\Capture; D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin; D:\altera\quartus60\bin; D:\altera\quartus60\win; D:\Program Files\ATI Technologies\ATI.ACE\Core-Static; d:\program files\Modeltech_6.1f\win32; D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib; D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib |
D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt; D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt; d:\ispLEVER_Classic1_7\ispcpld\bin; d:\ispLEVER_Classic1_7\ispFPGA\bin\nt; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin; D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin; D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib; D:\ispTOOLS8_1\ispcpld\bin; D:\ispTOOLS8_1\ispLeverDSP; D:\ispTOOLS8_1\ispFPGA\bin\nt; D:\ispTOOLS8_1\ispFPGA\data; D:\ispTOOLS8_1\active-hdl\bin; D:/Program Files/Texas Instruments/xdctools_3_16_02_32; D:\Program Files\ARM\ADSv1_2\bin; D:\Program Files\AMD APP\bin\x86; D:\WINDOWS\system32; D:\WINDOWS; D:\WINDOWS\System32\Wbem; D:\Program Files\Common Files\Thunder Network\KanKan\Codecs; D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt; D:\Program Files\Cadence\SPB_16.3\tools\bin; D:\Program Files\Cadence\SPB_16.3\tools\fet\bin; D:\Program Files\Cadence\SPB_16.3\tools\Capture; D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin; D:\altera\quartus60\bin; D:\altera\quartus60\win; D:\Program Files\ATI Technologies\ATI.ACE\Core-Static; d:\program files\Modeltech_6.1f\win32; D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib; D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib |
XILINX | < data not available > | D:\Xilinx\12.3\ISE_DS\ISE\ | D:\Xilinx\12.3\ISE_DS\ISE\ | D:\Xilinx\12.3\ISE_DS\ISE\ |
Translation Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-intstyle | ise | None | |
-dd | _ngo | None | |
-p | xc3s500e-pq208-4 | None | |
-uc | io_test.ucf | None |
Map Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ir | Use RLOC Constraints | OFF | OFF |
-cm | Optimization Strategy (Cover Mode) | area | area |
-intstyle | ise | None | |
-o | io_test_map.ncd | None | |
-pr | Pack I/O Registers/Latches into IOBs | off | off |
-p | xc3s500e-pq208-4 | None |
Place and Route Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-t | 1 | 1 | |
-intstyle | ise | ||
-ol | Place & Route Effort Level (Overall) | high | std |
-w | true | false |
Operating System Information | ||||
Operating System Information | xst | ngdbuild | map | par |
CPU Architecture/Speed | < data not available > | Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz | Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz | Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz |
Host | < data not available > | tony | tony | tony |
OS Name | < data not available > | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional |
OS Release | < data not available > | Service Pack 3 (build 2600) | Service Pack 3 (build 2600) | Service Pack 3 (build 2600) |