i2c_eeprom Project Status (09/26/2013 - 10:04:40)
Project File: i2c_eeprom_app.xise Parser Errors: No Errors
Module Name: i2c_eeprom_app Implementation State: Programming File Not Generated
Target Device: xc3s500e-5pq208
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 243 4656 5%
Number of Slice Flip Flops 256 9312 2%
Number of 4 input LUTs 443 9312 4%
Number of bonded IOBs 4 158 2%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期四 九月 26 09:57:45 2013   
Translation ReportCurrent星期四 九月 26 09:57:49 2013   
Map ReportOut of Date星期五 九月 20 23:25:12 2013   
Place and Route ReportOut of Date星期五 九月 20 23:25:30 2013   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of Date星期五 九月 20 23:25:33 2013   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent星期四 九月 26 10:04:39 2013

Date Generated: 09/26/2013 - 10