Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) dff44e278ad145cab69bb67d00d84107.33445E6619F442B3893122310496DA54.2 Target Package: pq208
Registration ID No user information available. Target Speed: -5
Date Generated 2014-09-21T13:56:15 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz CPU Speed 2195 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 28-bit up counter=1
ROMs=1
  • 16x8-bit ROM=1
Registers=8
  • Flip-Flops=8
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=18
  • NUM_4_INPUT_LUT=35
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=10
  • NUM_BUFGMUX=1
  • NUM_CYMUX=27
  • NUM_IOB_FF=1
  • NUM_LUT_RT=27
  • NUM_SLICEL=18
  • NUM_SLICE_FF=35
  • NUM_XOR=28
NetStatistics
  • NumNets_Active=63
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=19
  • NumNodesOfType_Active_CNTRLPIN=19
  • NumNodesOfType_Active_DOUBLE=60
  • NumNodesOfType_Active_DUMMY=58
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=9
  • NumNodesOfType_Active_HUNIHEX=4
  • NumNodesOfType_Active_INPUT=77
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=38
  • NumNodesOfType_Active_OUTPUT=49
  • NumNodesOfType_Active_PREBXBY=4
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=1
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=1
SiteStatistics
  • IBUF-DIFFMI=1
  • IBUF-DIFFSI=1
  • IOB-DIFFM=5
  • IOB-DIFFS=5
  • SLICEL-SLICEM=2
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=10
  • IOB_OFF1=1
  • IOB_OUTBUF=10
  • IOB_PAD=10
  • SLICEL=18
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=14
  • SLICEL_CYMUXG=13
  • SLICEL_F=17
  • SLICEL_FFX=17
  • SLICEL_FFY=18
  • SLICEL_G=18
  • SLICEL_GNDF=13
  • SLICEL_GNDG=13
  • SLICEL_XORF=14
  • SLICEL_XORG=14
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:2]
IOB
  • O1=[O1_INV:0] [O1:10]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:1]
  • SR=[SR:0] [SR_INV:1]
IOB_OFF1
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF1_INIT_ATTR=[INIT0:1]
  • OFF1_SR_ATTR=[SRLOW:1]
  • OFFATTRBOX=[ASYNC:1]
  • SR=[SR:0] [SR_INV:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:10]
IOB_PAD
  • DRIVEATTRBOX=[12:10]
  • IOATTRBOX=[LVCMOS25:10]
  • SLEW=[SLOW:10]
SLICEL
  • BX=[BX_INV:0] [BX:1]
  • CIN=[CIN_INV:0] [CIN:13]
  • CLK=[CLK:18] [CLK_INV:0]
  • SR=[SR:0] [SR_INV:18]
SLICEL_CYMUXF
  • 0=[0:14] [0_INV:0]
  • 1=[1_INV:0] [1:14]
SLICEL_CYMUXG
  • 0=[0:13] [0_INV:0]
SLICEL_FFX
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:17]
  • FFX_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SR=[SR:0] [SR_INV:17]
  • SYNC_ATTR=[ASYNC:17]
SLICEL_FFY
  • CK=[CK:18] [CK_INV:0]
  • D=[D:18] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:18]
  • FFY_SR_ATTR=[SRLOW:18]
  • LATCH_OR_FF=[FF:18]
  • SR=[SR:0] [SR_INV:18]
  • SYNC_ATTR=[ASYNC:18]
SLICEL_XORF
  • 1=[1_INV:0] [1:14]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=2
  • PAD=2
IBUF_INBUF
  • IN=2
  • OUT=2
IBUF_PAD
  • PAD=2
IOB
  • O1=10
  • OTCLK1=1
  • PAD=10
  • SR=1
IOB_OFF1
  • CK=1
  • D=1
  • Q=1
  • SR=1
IOB_OUTBUF
  • IN=10
  • OUT=10
IOB_PAD
  • PAD=10
SLICEL
  • BX=1
  • CIN=13
  • CLK=18
  • COUT=13
  • F1=17
  • F2=3
  • F3=3
  • F4=3
  • G1=18
  • G2=4
  • G3=4
  • G4=4
  • SR=18
  • XQ=17
  • YQ=18
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=14
  • 1=14
  • OUT=14
  • S0=14
SLICEL_CYMUXG
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_F
  • A1=17
  • A2=3
  • A3=3
  • A4=3
  • D=17
SLICEL_FFX
  • CK=17
  • D=17
  • Q=17
  • SR=17
SLICEL_FFY
  • CK=18
  • D=18
  • Q=18
  • SR=18
SLICEL_G
  • A1=18
  • A2=4
  • A3=4
  • A4=4
  • D=18
SLICEL_GNDF
  • 0=13
SLICEL_GNDG
  • 0=13
SLICEL_XORF
  • 0=14
  • 1=14
  • O=14
SLICEL_XORG
  • 0=14
  • 1=14
  • O=14
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
XSLTProcess 1 1 0 0 0 0 0
_impact 39 36 0 0 0 0 0
bitgen 4 4 0 0 0 0 0
cpldfit 1 1 0 0 0 0 0
hprep6 1 1 0 0 0 0 0
map 4 4 0 0 0 0 0
ngdbuild 8 8 0 0 0 0 0
par 4 4 0 0 0 0 0
taengine 1 1 0 0 0 0 0
trce 4 4 0 0 0 0 0
tsim 1 1 0 0 0 0 0
xst 5 5 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-09-21T09:08:07
PROP_intWbtProjectID=33445E6619F442B3893122310496DA54 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgCfg_Unused=Float PROP_AutoTop=true
PROP_CompxlibEdkSimLib=false PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=pq208 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=36 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=27 NGDBUILD_NUM_LUT4=7 NGDBUILD_NUM_MUXCY=27
NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=28
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=36 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=27 NGDBUILD_NUM_LUT4=7
NGDBUILD_NUM_MUXCY=27 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=28
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-5-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5