beep Project Status (09/26/2013 - 08:43:55)
Project File: beep.xise Parser Errors: No Errors
Module Name: beep Implementation State: Programming File Generated
Target Device: xc3s500e-5pq208
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
3 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 27 9,312 1%  
Number of 4 input LUTs 1 9,312 1%  
Number of occupied Slices 14 4,656 1%  
    Number of Slices containing only related logic 14 14 100%  
    Number of Slices containing unrelated logic 0 14 0%  
Total Number of 4 input LUTs 26 9,312 1%  
    Number used as logic 1      
    Number used as a route-thru 25      
Number of bonded IOBs 3 158 1%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.68      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期五 九月 20 22:55:33 201303 Warnings (3 new)0
Translation ReportCurrent星期四 九月 26 08:43:11 2013000
Map ReportCurrent星期四 九月 26 08:43:24 2013002 Infos (0 new)
Place and Route ReportCurrent星期四 九月 26 08:43:43 2013003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent星期四 九月 26 08:43:48 2013005 Infos (0 new)
Bitgen ReportCurrent星期四 九月 26 08:43:55 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent星期四 九月 26 08:43:55 2013

Date Generated: 09/26/2013