irda_led_7_seg_app Project Status (09/21/2013 - 09:01:03)
Project File: irda_led_7_seg_app.xise Parser Errors: No Errors
Module Name: irda_led_7_seg_app Implementation State: Programming File Generated
Target Device: xc3s500e-5pq208
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
551 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 94 9,312 1%  
Number of 4 input LUTs 91 9,312 1%  
Number of occupied Slices 68 4,656 1%  
    Number of Slices containing only related logic 68 68 100%  
    Number of Slices containing unrelated logic 0 68 0%  
Total Number of 4 input LUTs 113 9,312 1%  
    Number used as logic 91      
    Number used as a route-thru 22      
Number of bonded IOBs 13 158 8%  
    IOB Flip Flops 1      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.45      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期六 九月 21 08:59:44 20130551 Warnings (0 new)2 Infos (0 new)
Translation ReportCurrent星期六 九月 21 08:59:49 2013000
Map ReportCurrent星期六 九月 21 08:59:55 2013002 Infos (2 new)
Place and Route ReportCurrent星期六 九月 21 09:00:11 2013003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrent星期六 九月 21 09:00:15 2013005 Infos (5 new)
Bitgen ReportCurrent星期六 九月 21 09:01:02 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent星期六 九月 21 09:01:03 2013

Date Generated: 09/21/2013