led_7_seg_app Project Status (09/26/2013 - 09:52:34)
Project File: led_7_seg_app.xise Parser Errors: No Errors
Module Name: led_7_seg_app Implementation State: Programming File Generated
Target Device: xc3s500e-5pq208
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
62 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 65 9,312 1%  
Number of 4 input LUTs 13 9,312 1%  
Number of occupied Slices 35 4,656 1%  
    Number of Slices containing only related logic 35 35 100%  
    Number of Slices containing unrelated logic 0 35 0%  
Total Number of 4 input LUTs 62 9,312 1%  
    Number used as logic 13      
    Number used as a route-thru 49      
Number of bonded IOBs 12 158 7%  
    IOB Flip Flops 1      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.13      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期四 九月 26 09:52:02 2013062 Warnings (0 new)1 Info (0 new)
Translation ReportCurrent星期四 九月 26 09:52:06 2013000
Map ReportCurrent星期四 九月 26 09:52:11 2013002 Infos (0 new)
Place and Route ReportCurrent星期四 九月 26 09:52:25 2013003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent星期四 九月 26 09:52:28 2013005 Infos (0 new)
Bitgen ReportCurrent星期四 九月 26 09:52:33 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent星期四 九月 26 09:52:33 2013

Date Generated: 09/26/2013