i2c_eeprom_app Project Status
Project File: i2c_eeprom_app.xise Parser Errors: No Errors
Module Name: i2c_eeprom_app Implementation State: Placed and Routed
Target Device: xc3s500e-5pq208
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 270 9,312 2%  
Number of 4 input LUTs 417 9,312 4%  
Number of occupied Slices 267 4,656 5%  
    Number of Slices containing only related logic 267 267 100%  
    Number of Slices containing unrelated logic 0 267 0%  
Total Number of 4 input LUTs 454 9,312 4%  
    Number used as logic 417      
    Number used as a route-thru 37      
Number of bonded IOBs 4 158 2%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.74      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期五 九月 20 23:23:59 20130211 Warnings (0 new)1 Info (0 new)
Translation ReportCurrent星期五 九月 20 23:25:04 2013000
Map ReportCurrent星期五 九月 20 23:25:12 2013   
Place and Route ReportCurrent星期五 九月 20 23:25:30 2013003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrent星期五 九月 20 23:25:33 2013005 Infos (5 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 09/21/2013 - 06:55:5