System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
d:\ispLEVER_Classic1_7\ispcpld\bin;
d:\ispLEVER_Classic1_7\ispFPGA\bin\nt;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;
D:\ispTOOLS8_1\ispcpld\bin;
D:\ispTOOLS8_1\ispLeverDSP;
D:\ispTOOLS8_1\ispFPGA\bin\nt;
D:\ispTOOLS8_1\ispFPGA\data;
D:\ispTOOLS8_1\active-hdl\bin;
D:/Program Files/Texas Instruments/xdctools_3_16_02_32;
D:\Program Files\ARM\ADSv1_2\bin;
D:\Program Files\AMD APP\bin\x86;
D:\WINDOWS\system32;
D:\WINDOWS;
D:\WINDOWS\System32\Wbem;
D:\Program Files\Common Files\Thunder Network\KanKan\Codecs;
D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
D:\Program Files\Cadence\SPB_16.3\tools\bin;
D:\Program Files\Cadence\SPB_16.3\tools\fet\bin;
D:\Program Files\Cadence\SPB_16.3\tools\Capture;
D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin;
D:\altera\quartus60\bin;
D:\altera\quartus60\win;
D:\Program Files\ATI Technologies\ATI.ACE\Core-Static;
d:\program files\Modeltech_6.1f\win32;
D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib;
D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib
D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
d:\ispLEVER_Classic1_7\ispcpld\bin;
d:\ispLEVER_Classic1_7\ispFPGA\bin\nt;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;
D:\ispTOOLS8_1\ispcpld\bin;
D:\ispTOOLS8_1\ispLeverDSP;
D:\ispTOOLS8_1\ispFPGA\bin\nt;
D:\ispTOOLS8_1\ispFPGA\data;
D:\ispTOOLS8_1\active-hdl\bin;
D:/Program Files/Texas Instruments/xdctools_3_16_02_32;
D:\Program Files\ARM\ADSv1_2\bin;
D:\Program Files\AMD APP\bin\x86;
D:\WINDOWS\system32;
D:\WINDOWS;
D:\WINDOWS\System32\Wbem;
D:\Program Files\Common Files\Thunder Network\KanKan\Codecs;
D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
D:\Program Files\Cadence\SPB_16.3\tools\bin;
D:\Program Files\Cadence\SPB_16.3\tools\fet\bin;
D:\Program Files\Cadence\SPB_16.3\tools\Capture;
D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin;
D:\altera\quartus60\bin;
D:\altera\quartus60\win;
D:\Program Files\ATI Technologies\ATI.ACE\Core-Static;
d:\program files\Modeltech_6.1f\win32;
D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib;
D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib
D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
d:\ispLEVER_Classic1_7\ispcpld\bin;
d:\ispLEVER_Classic1_7\ispFPGA\bin\nt;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;
D:\ispTOOLS8_1\ispcpld\bin;
D:\ispTOOLS8_1\ispLeverDSP;
D:\ispTOOLS8_1\ispFPGA\bin\nt;
D:\ispTOOLS8_1\ispFPGA\data;
D:\ispTOOLS8_1\active-hdl\bin;
D:/Program Files/Texas Instruments/xdctools_3_16_02_32;
D:\Program Files\ARM\ADSv1_2\bin;
D:\Program Files\AMD APP\bin\x86;
D:\WINDOWS\system32;
D:\WINDOWS;
D:\WINDOWS\System32\Wbem;
D:\Program Files\Common Files\Thunder Network\KanKan\Codecs;
D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
D:\Program Files\Cadence\SPB_16.3\tools\bin;
D:\Program Files\Cadence\SPB_16.3\tools\fet\bin;
D:\Program Files\Cadence\SPB_16.3\tools\Capture;
D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin;
D:\altera\quartus60\bin;
D:\altera\quartus60\win;
D:\Program Files\ATI Technologies\ATI.ACE\Core-Static;
d:\program files\Modeltech_6.1f\win32;
D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib;
D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib
D:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
D:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
d:\ispLEVER_Classic1_7\ispcpld\bin;
d:\ispLEVER_Classic1_7\ispFPGA\bin\nt;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin;
D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;
D:\ispTOOLS8_1\ispcpld\bin;
D:\ispTOOLS8_1\ispLeverDSP;
D:\ispTOOLS8_1\ispFPGA\bin\nt;
D:\ispTOOLS8_1\ispFPGA\data;
D:\ispTOOLS8_1\active-hdl\bin;
D:/Program Files/Texas Instruments/xdctools_3_16_02_32;
D:\Program Files\ARM\ADSv1_2\bin;
D:\Program Files\AMD APP\bin\x86;
D:\WINDOWS\system32;
D:\WINDOWS;
D:\WINDOWS\System32\Wbem;
D:\Program Files\Common Files\Thunder Network\KanKan\Codecs;
D:\Program Files\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
D:\Program Files\Cadence\SPB_16.3\tools\bin;
D:\Program Files\Cadence\SPB_16.3\tools\fet\bin;
D:\Program Files\Cadence\SPB_16.3\tools\Capture;
D:\Program Files\Cadence\SPB_16.3\tools\pcb\bin;
D:\altera\quartus60\bin;
D:\altera\quartus60\win;
D:\Program Files\ATI Technologies\ATI.ACE\Core-Static;
d:\program files\Modeltech_6.1f\win32;
D:\Program Files\MentorGraphics\9.4PADS\SDD_HOME\common\win32\lib;
D:\Program Files\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib
XILINX D:\Xilinx\12.3\ISE_DS\ISE\ D:\Xilinx\12.3\ISE_DS\ISE\ D:\Xilinx\12.3\ISE_DS\ISE\ D:\Xilinx\12.3\ISE_DS\ISE\
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   beep.prj  
-ifmt   mixed MIXED
-ofn   beep  
-ofmt   NGC NGC
-p   xc3s500e-5-pq208  
-top   beep  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   24 24
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc3s500e-pq208-5 None
-uc   beep.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ir Use RLOC Constraints OFF OFF
-cm Optimization Strategy (Cover Mode) area area
-intstyle   ise None
-o   beep_map.ncd None
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc3s500e-pq208-5 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-t   1 1
-intstyle   ise  
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3169 MHz Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3168 MHz
Host tony tony tony tony
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600)