led Project Status (09/21/2013 - 09:20:48)
Project File: led_sw_key.xise Parser Errors: No Errors
Module Name: led Implementation State: Programming File Generated
Target Device: xc3s500e-5pq208
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 6 158 3%  
    IOB Flip Flops 2      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 0.67      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期六 九月 21 09:20:23 201301 Warning (0 new)0
Translation ReportCurrent星期六 九月 21 09:20:27 2013000
Map ReportCurrent星期六 九月 21 09:20:31 2013002 Infos (0 new)
Place and Route ReportCurrent星期六 九月 21 09:20:40 2013001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent星期六 九月 21 09:20:43 2013005 Infos (0 new)
Bitgen ReportCurrent星期六 九月 21 09:20:47 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent星期六 九月 21 09:20:48 2013

Date Generated: 09/21/2013