led_7_seg Project Status (09/21/2014 - 13:56:33)
Project File: led_7_seg_static.xise Parser Errors: No Errors
Module Name: led_7_seg Implementation State: Programming File Generated
Target Device: xc3s500e-5pq208
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
6 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 35 9,312 1%  
Number of 4 input LUTs 8 9,312 1%  
Number of occupied Slices 18 4,656 1%  
    Number of Slices containing only related logic 18 18 100%  
    Number of Slices containing unrelated logic 0 18 0%  
Total Number of 4 input LUTs 35 9,312 1%  
    Number used as logic 8      
    Number used as a route-thru 27      
Number of bonded IOBs 12 158 7%  
    IOB Flip Flops 1      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.27      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent日 9 21 13:54:48 201406 Warnings (0 new)0
Translation ReportCurrent日 9 21 13:55:03 2014000
Map ReportCurrent日 9 21 13:55:17 2014002 Infos (0 new)
Place and Route ReportCurrent日 9 21 13:55:49 2014002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent日 9 21 13:55:58 2014005 Infos (0 new)
Bitgen ReportCurrent日 9 21 13:56:14 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent日 9 21 13:56:16 2014
WebTalk Log FileCurrent日 9 21 13:56:33 2014

Date Generated: 09/21/2014 - 13:56:33