ispLEVER Classic 1.7.00.05.28.13 Fitter Report File
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Project_Summary
Project Name : led_key
Project Path : J:\LC4256\led_key\par
Project Fitted on : Fri Sep 16 11:57:47 2011
Device : M4256_64
Package : 100
GLB Input Mux Size : 33
Available Blocks : 16
Speed : -10
Part Number : LC4256V-10T100I
Source Format : Pure_Verilog_HDL
Project 'led_key' Fit Successfully!
Compilation_Times
Prefit Time 0 secs
Load Design Time 1.05 secs
Partition Time 0.00 secs
Place Time 0.00 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
Total Input Pins 6
Total Logic Functions 4
Total Output Pins 4
Total Bidir I/O Pins 0
Total Buried Nodes 0
Total Flip-Flops 4
Total D Flip-Flops 4
Total T Flip-Flops 0
Total Latches 0
Total Product Terms 12
Total Reserved Pins 0
Total Locked Pins 10
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 0
Total Unique Resets 1
Total Unique Presets 0
Fmax Logic Levels -
Device_Resource_Summary
Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 2 2 --> 50
Input-Only Pins 6 0 6 --> 0
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 62 8 54 --> 12
Logic Functions 256 4 252 --> 1
Input Registers 64 0 64 --> 0
GLB Inputs 576 6 570 --> 1
Logical Product Terms 1280 4 1276 --> 0
Occupied GLBs 16 3 13 --> 18
Macrocells 256 4 252 --> 1
Control Product Terms:
GLB Clock/Clock Enables 16 0 16 --> 0
GLB Reset/Presets 16 0 16 --> 0
Macrocell Clocks 256 0 256 --> 0
Macrocell Clock Enables 256 0 256 --> 0
Macrocell Enables 256 0 256 --> 0
Macrocell Resets 256 0 256 --> 0
Macrocell Presets 256 0 256 --> 0
Global Routing Pool 324 5 319 --> 1
GRP from IFB .. 5 .. --> ..
(from input signals) .. 5 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 0 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
GLB_Resource_Summary
# of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
-------------------------------------------------------------------------------------------
GLB A 0 0 0 0/4 0 0 0 16 0 0
GLB B 0 0 0 0/4 0 0 0 16 0 0
GLB C 0 0 0 0/4 0 0 0 16 0 0
GLB D 0 0 0 0/4 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB E 0 0 0 0/4 0 0 0 16 0 0
GLB F 0 0 0 0/4 0 0 0 16 0 0
GLB G 0 0 0 0/4 0 0 0 16 0 0
GLB H 0 0 0 0/4 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB I 0 0 0 0/4 0 0 0 16 0 0
GLB J 0 0 0 1/4 0 0 0 16 0 0
GLB K 2 0 2 4/4 0 1 0 15 1 1
GLB L 3 1 4 3/4 0 3 0 13 3 3
-------------------------------------------------------------------------------------------
GLB M 0 0 0 0/4 0 0 0 16 0 0
GLB N 0 0 0 0/4 0 0 0 16 0 0
GLB O 0 0 0 0/4 0 0 0 16 0 0
GLB P 0 0 0 0/4 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
TOTALS: 5 1 6 8/64 0 4 0 252 4 4
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB I 0 0 0 0 0 0 0
GLB J 0 0 0 0 0 0 0
GLB K 0 0 0 0 0 0 0
GLB L 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB M 0 0 0 0 0 0 0
GLB N 0 0 0 0 0 0 0
GLB O 0 0 0 0 0 0 0
GLB P 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
--------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 | I_O | 0 |C12 | | | |
4 | I_O | 0 |C10 | | | |
5 | I_O | 0 |C6 | | | |
6 | I_O | 0 |C2 | | | |
7 |GNDIO0 | - | | | | |
8 | I_O | 0 |D12 | | | |
9 | I_O | 0 |D10 | | | |
10 | I_O | 0 |D6 | | | |
11 | I_O | 0 |D4 | | | |
12 | IN0 | 0 | | | | |
13 |VCCIO0 | - | | | | |
14 | I_O | 0 |E4 | | | |
15 | I_O | 0 |E6 | | | |
16 | I_O | 0 |E10 | | | |
17 | I_O | 0 |E12 | | | |
18 |GNDIO0 | - | | | | |
19 | I_O | 0 |F2 | | | |
20 | I_O | 0 |F6 | | | |
21 | I_O | 0 |F10 | | | |
22 | I_O | 0 |F12 | | | |
23 | IN1 | 0 | | | | |
24 | TCK | - | | | | |
25 | VCC | - | | | | |
26 | GND | - | | | | |
27 | IN2 | 0 | | | | |
28 | I_O | 0 |G12 | | | |
29 | I_O | 0 |G10 | | | |
30 | I_O | 0 |G6 | | | |
31 | I_O | 0 |G2 | | | |
32 |GNDIO0 | - | | | | |
33 |VCCIO0 | - | | | | |
34 | I_O | 0 |H12 | | | |
35 | I_O | 0 |H10 | | | |
36 | I_O | 0 |H6 | | | |
37 | I_O | 0 |H2 | | | |
38 |INCLK1 | 0 | | | | |
39 |INCLK2 | 1 | | | | |
40 | VCC | - | | | | |
41 | I_O | 1 |I2 | | | |
42 | I_O | 1 |I6 | | | |
43 | I_O | 1 |I10 | | | |
44 | I_O | 1 |I12 | | | |
45 |VCCIO1 | - | | | | |
46 |GNDIO1 | - | | | | |
47 | I_O | 1 |J2 | | | |
48 | I_O | 1 |J6 | | | |
49 | I_O | 1 |J10 | | | |
50 | I_O | 1 |J12 | * |LVCMOS18 | Input |skey_0_
51 | GND | - | | | | |
52 | TMS | - | | | | |
53 | I_O | 1 |K12 | * |LVCMOS18 | Input |skey_1_
54 | I_O | 1 |K10 | * |LVCMOS18 | Input |skey_2_
55 | I_O | 1 |K6 | * |LVCMOS18 | Input |skey_3_
56 | I_O | 1 |K2 | * |LVCMOS18 | Output|led_0_
57 |GNDIO1 | - | | | | |
58 | I_O | 1 |L12 | * |LVCMOS18 | Output|led_1_
59 | I_O | 1 |L10 | * |LVCMOS18 | Output|led_2_
60 | I_O | 1 |L6 | * |LVCMOS18 | Output|led_3_
61 | I_O | 1 |L4 | | | |
62 | IN3 | 1 | | | | |
63 |VCCIO1 | - | | | | |
64 | I_O | 1 |M4 | | | |
65 | I_O | 1 |M6 | | | |
66 | I_O | 1 |M10 | | | |
67 | I_O | 1 |M12 | | | |
68 |GNDIO1 | - | | | | |
69 | I_O | 1 |N2 | | | |
70 | I_O | 1 |N6 | | | |
71 | I_O | 1 |N10 | | | |
72 | I_O | 1 |N12 | | | |
73 | IN4 | 1 | | | | |
74 | TDO | - | | | | |
75 | VCC | - | | | | |
76 | GND | - | | | | |
77 | IN5 | 1 | | | | |
78 | I_O | 1 |O12 | | | |
79 | I_O | 1 |O10 | | | |
80 | I_O | 1 |O6 | | | |
81 | I_O | 1 |O2 | | | |
82 |GNDIO1 | - | | | | |
83 |VCCIO1 | - | | | | |
84 | I_O | 1 |P12 | | | |
85 | I_O | 1 |P10 | | | |
86 | I_O | 1 |P6 | | | |
87 | I_O/OE| 1 |P2 | | | |
88 |INCLK3 | 1 | | * |LVCMOS18 | Input |reset_n
89 |INCLK0 | 0 | | * |LVCMOS18 | Input |clk
90 | VCC | - | | | | |
91 | I_O/OE| 0 |A2 | | | |
92 | I_O | 0 |A6 | | | |
93 | I_O | 0 |A10 | | | |
94 | I_O | 0 |A12 | | | |
95 |VCCIO0 | - | | | | |
96 |GNDIO0 | - | | | | |
97 | I_O | 0 |B2 | | | |
98 | I_O | 0 |B6 | | | |
99 | I_O | 0 |B10 | | | |
100 | I_O | 0 |B12 | | | |
--------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
Input_Signal_List
Input
Pin Fanout
Pin GLB Type Pullup Signal
--------------------------------------------------
89 -- INCLK ---------------- Up clk
88 -- INCLK 2 ----------KL---- Up reset_n
50 J I/O 1 ----------K----- Up skey_0_
53 K I/O 1 -----------L---- Up skey_1_
54 K I/O 1 -----------L---- Up skey_2_
55 K I/O 1 -----------L---- Up skey_3_
--------------------------------------------------
Output_Signal_List
I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-------------------------------------------------------------------------------
56 K 2 - 1 1 DFF * R ---------------- Fast Up led_0_
58 L 2 - 1 1 DFF * R ---------------- Fast Up led_1_
59 L 2 - 1 1 DFF * R ---------------- Fast Up led_2_
60 L 2 - 1 1 DFF * R ---------------- Fast Up led_3_
-------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Bidir_Signal_List
I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Buried_Signal_List
PostFit_Equations
led_0_.D = !skey_0_ ; (1 pterm, 1 signal)
led_0_.C = clk ; (1 pterm, 1 signal)
led_0_.AR = !reset_n ; (1 pterm, 1 signal)
led_1_.D = !skey_1_ ; (1 pterm, 1 signal)
led_1_.C = clk ; (1 pterm, 1 signal)
led_1_.AR = !reset_n ; (1 pterm, 1 signal)
led_2_.D = !skey_2_ ; (1 pterm, 1 signal)
led_2_.C = clk ; (1 pterm, 1 signal)
led_2_.AR = !reset_n ; (1 pterm, 1 signal)
led_3_.D = !skey_3_ ; (1 pterm, 1 signal)
led_3_.C = clk ; (1 pterm, 1 signal)
led_3_.AR = !reset_n ; (1 pterm, 1 signal)