#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 #install: d:\ispLEVER_Classic2_0\synpbase #OS: Windows XP 5.1 #Hostname: TONY #Implementation: par_lc4128v $ Start of Compile #Fri Dec 30 13:28:50 2011 Synopsys Verilog Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N: : | Running in 32-bit mode Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\umr_capim.v" @I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\scemi_objects.v" @I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\scemi_pipes.svh" @I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\hypermods.v" @I::"d:\ispLEVER_Classic2_0\ispcpld\..\cae_library\synthesis\verilog\mach.v" @I::"J:\my_workspace\led_7_seg_app\par_lc4128v\led_7_seg_app.h" @I::"J:\my_workspace\led_7_seg\rtl\led_7_seg.v" @I::"J:\my_workspace\led_7_seg_app\rtl\led_7_seg_app.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module led_7_seg_app @N:CG364 : led_7_seg.v(29) | Synthesizing module led_7_seg @W:CL271 : led_7_seg.v(74) | Pruning bits 17 to 0 of cnt_1d[18:0] -- not in use ... @W:CL208 : led_7_seg.v(130) | All reachable assignments to bit 4 of disp_data_r[7:0] assign 0, register removed by optimization. @W:CL208 : led_7_seg.v(130) | All reachable assignments to bit 5 of disp_data_r[7:0] assign 0, register removed by optimization. @W:CL208 : led_7_seg.v(130) | All reachable assignments to bit 6 of disp_data_r[7:0] assign 0, register removed by optimization. @W:CL208 : led_7_seg.v(130) | All reachable assignments to bit 7 of disp_data_r[7:0] assign 0, register removed by optimization. @N:CG364 : led_7_seg_app.v(24) | Synthesizing module led_7_seg_app @END At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 37MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Dec 30 13:28:50 2011 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @N: : | Running in 32-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 36MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Dec 30 13:28:52 2011 ###########################################################] Map & Optimize Report Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N:MF249 : | Running in 32-bit mode. @N:MO106 : led_7_seg.v(93) | Found ROM, 'seg_2[6:0]', 16 words by 7 bits --------------------------------------- Resource Usage Report Simple gate primitives: DFFRH 64 uses DFFSH 2 uses IBUF 2 uses OBUF 10 uses AND2 95 uses INV 39 uses XOR2 50 uses OR2 5 uses @N:FC100 : | Timing Report not generated for this device, please use place and route tools for timing analysis. I-2014.03LC Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 25MB peak: 59MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Dec 30 13:28:52 2011 ###########################################################]