#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: d:\ispLEVER_Classic2_0\synpbase
#OS: Windows XP 5.1
#Hostname: TONY

#Implementation: par_lc4128v

$ Start of Compile
#Fri Dec 30 12:59:10 2011

Synopsys Verilog Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\umr_capim.v"
@I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\scemi_objects.v"
@I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\scemi_pipes.svh"
@I::"d:\ispLEVER_Classic2_0\synpbase\lib\vlog\hypermods.v"
@I::"d:\ispLEVER_Classic2_0\ispcpld\..\cae_library\synthesis\verilog\mach.v"
@I::"J:\my_workspace\led_flash\par_lc4128v\led.h"
@I::"J:\my_workspace\led_flash\rtl\led.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module led
@N:CG364 : led.v(22) | Synthesizing module led

@W:CL190 : led.v(53) | Optimizing register bit cnt[27] to a constant 0
@W:CL190 : led.v(53) | Optimizing register bit cnt[28] to a constant 0
@W:CL190 : led.v(53) | Optimizing register bit cnt[29] to a constant 0
@W:CL190 : led.v(53) | Optimizing register bit cnt[30] to a constant 0
@W:CL190 : led.v(53) | Optimizing register bit cnt[31] to a constant 0
@W:CL279 : led.v(53) | Pruning register bits 31 to 27 of cnt[31:0] 

@W:CL260 : led.v(63) | Pruning register bit 1 of led_flash[1:0] 

@END

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 37MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 30 12:59:10 2011

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Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: :  | Running in 32-bit mode 

Linker output is up to date. No re-linking necessary


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 36MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 30 12:59:12 2011

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Map & Optimize Report

Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC 
@N:MF249 :  | Running in 32-bit mode. 
---------------------------------------
Resource Usage Report

Simple gate primitives:
DFFRH           27 uses
DFFCRH          1 use
IBUF            2 uses
OBUF            2 uses
AND2            81 uses
INV             25 uses
XOR2            26 uses


@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
I-2014.03LC 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 25MB peak: 60MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 30 12:59:12 2011

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