ispLEVER Classic 1.7.00.05.28.13 Fitter Report File

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Project Name : led_7_seg_app Project Path : J:\LC4256\led_7_seg_app\par Project Fitted on : Fri Sep 16 11:48:24 2011 Device : M4256_64 Package : 100 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -7.5 Part Number : LC4256V-75T100C Source Format : Pure_Verilog_HDL Project 'led_7_seg_app' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 1.02 secs Partition Time 0.13 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 2 Total Logic Functions 79 Total Output Pins 12 Total Bidir I/O Pins 0 Total Buried Nodes 67 Total Flip-Flops 78 Total D Flip-Flops 30 Total T Flip-Flops 48 Total Latches 0 Total Product Terms 281 Total Reserved Pins 0 Total Locked Pins 14 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 1 Total Unique Clock Enables 0 Total Unique Resets 1 Total Unique Presets 1 Fmax Logic Levels 2 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 2 2 --> 50 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 62 12 50 --> 19 Logic Functions 256 79 177 --> 30 Input Registers 64 0 64 --> 0 GLB Inputs 576 153 423 --> 26 Logical Product Terms 1280 125 1155 --> 9 Occupied GLBs 16 11 5 --> 68 Macrocells 256 79 177 --> 30 Control Product Terms: GLB Clock/Clock Enables 16 0 16 --> 0 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 0 256 --> 0 Macrocell Clock Enables 256 0 256 --> 0 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 0 256 --> 0 Macrocell Presets 256 0 256 --> 0 Global Routing Pool 324 68 256 --> 20 GRP from IFB .. 1 .. --> .. (from input signals) .. 1 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 67 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 3 24 27 0/4 0 14 0 2 15 14 GLB B 1 24 25 0/4 0 10 0 6 12 10 GLB C 1 4 5 0/4 0 3 0 13 8 3 GLB D 0 0 0 0/4 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- GLB E 0 0 0 0/4 0 0 0 16 0 0 GLB F 0 0 0 0/4 0 0 0 16 0 0 GLB G 5 0 5 1/4 0 1 0 15 4 1 GLB H 0 5 5 4/4 0 4 0 12 10 4 ------------------------------------------------------------------------------------------- GLB I 6 3 9 4/4 0 5 0 11 9 5 GLB J 2 5 7 3/4 0 3 0 13 9 3 GLB K 1 19 20 0/4 0 14 0 2 15 14 GLB L 11 6 17 0/4 0 5 0 11 10 5 ------------------------------------------------------------------------------------------- GLB M 3 9 12 0/4 0 6 0 10 10 6 GLB N 1 20 21 0/4 0 14 0 2 23 14 GLB O 0 0 0 0/4 0 0 0 16 0 0 GLB P 0 0 0 0/4 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- TOTALS: 34 119 153 12/64 0 79 0 177 125 79 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB I 0 0 0 0 0 0 0 GLB J 0 0 0 0 0 0 0 GLB K 0 0 0 0 0 0 0 GLB L 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB M 0 0 0 0 0 0 0 GLB N 0 0 0 0 0 0 0 GLB O 0 0 0 0 0 0 0 GLB P 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ----------------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |C12 | | | | 4 | I_O | 0 |C10 | | | | 5 | I_O | 0 |C6 | | | | 6 | I_O | 0 |C2 | | | | 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |D12 | | | | 9 | I_O | 0 |D10 | | | | 10 | I_O | 0 |D6 | | | | 11 | I_O | 0 |D4 | | | | 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |E4 | | | | 15 | I_O | 0 |E6 | | | | 16 | I_O | 0 |E10 | | | | 17 | I_O | 0 |E12 | | | | 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |F2 | | | | 20 | I_O | 0 |F6 | | | | 21 | I_O | 0 |F10 | | | | 22 | I_O | 0 |F12 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |G12 | | | | 29 | I_O | 0 |G10 | | | | 30 | I_O | 0 |G6 | | | | 31 | I_O | 0 |G2 | * |LVCMOS18 | Output|seg_3_ 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |H12 | * |LVCMOS18 | Output|seg_4_ 35 | I_O | 0 |H10 | * |LVCMOS18 | Output|seg_2_ 36 | I_O | 0 |H6 | * |LVCMOS18 | Output|seg_7_ 37 | I_O | 0 |H2 | * |LVCMOS18 | Output|seg_6_ 38 |INCLK1 | 0 | | | | | 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |I2 | * |LVCMOS18 | Output|dig_0_ 42 | I_O | 1 |I6 | * |LVCMOS18 | Output|seg_0_ 43 | I_O | 1 |I10 | * |LVCMOS18 | Output|dig_3_ 44 | I_O | 1 |I12 | * |LVCMOS18 | Output|dig_2_ 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |J2 | * |LVCMOS18 | Output|seg_5_ 48 | I_O | 1 |J6 | * |LVCMOS18 | Output|dig_1_ 49 | I_O | 1 |J10 | * |LVCMOS18 | Output|seg_1_ 50 | I_O | 1 |J12 | | | | 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |K12 | | | | 54 | I_O | 1 |K10 | | | | 55 | I_O | 1 |K6 | | | | 56 | I_O | 1 |K2 | | | | 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |L12 | | | | 59 | I_O | 1 |L10 | | | | 60 | I_O | 1 |L6 | | | | 61 | I_O | 1 |L4 | | | | 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |M4 | | | | 65 | I_O | 1 |M6 | | | | 66 | I_O | 1 |M10 | | | | 67 | I_O | 1 |M12 | | | | 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |N2 | | | | 70 | I_O | 1 |N6 | | | | 71 | I_O | 1 |N10 | | | | 72 | I_O | 1 |N12 | | | | 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |O12 | | | | 79 | I_O | 1 |O10 | | | | 80 | I_O | 1 |O6 | | | | 81 | I_O | 1 |O2 | | | | 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |P12 | | | | 85 | I_O | 1 |P10 | | | | 86 | I_O | 1 |P6 | | | | 87 | I_O/OE| 1 |P2 | | | | 88 |INCLK3 | 1 | | * |LVCMOS18 | Input |reset_n 89 |INCLK0 | 0 | | * |LVCMOS18 | Input |clk 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A2 | | | | 92 | I_O | 0 |A6 | | | | 93 | I_O | 0 |A10 | | | | 94 | I_O | 0 |A12 | | | | 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |B2 | | | | 98 | I_O | 0 |B6 | | | | 99 | I_O | 0 |B10 | | | | 100 | I_O | 0 |B12 | | | | ----------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal -------------------------------------------------- 89 -- INCLK ---------------- Up clk 88 -- INCLK 11 ABC---GHIJKLMN-- Up reset_n -------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- 41 I 3 1 1 1 DFF * S ---------------- Fast Up dig_0_ 48 J 3 1 1 1 DFF * S ---------------- Fast Up dig_1_ 44 I 3 1 1 1 DFF * S ---------------- Fast Up dig_2_ 43 I 3 1 1 1 DFF * S ---------------- Fast Up dig_3_ 42 I 5 1 4 1 DFF * R ---------------- Fast Up seg_0_ 49 J 5 1 4 1 DFF * R ---------------- Fast Up seg_1_ 35 H 5 1 3 1 DFF * R ---------------- Fast Up seg_2_ 31 G 5 1 4 1 DFF * R ---------------- Fast Up seg_3_ 34 H 5 1 3 1 DFF * R ---------------- Fast Up seg_4_ 47 J 5 1 4 1 DFF * R ---------------- Fast Up seg_5_ 37 H 5 1 3 1 DFF * R ---------------- Fast Up seg_6_ 36 H 1 - 1 1 DFF * R ---------------- Fast Up seg_7_ ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ----------------------------------------------------------------------------------- 13 A 23 - 1 1 COM 2 ------------MN-- N_48 10 C 2 1 1 1 DFF * R 3 ABC------------- cnt_0_ 9 B 11 1 1 1 TFF * R 2 AB-------------- cnt_10_ 1 A 12 1 1 1 TFF * R 2 AB-------------- cnt_11_ 2 A 13 1 1 1 TFF * R 2 AB-------------- cnt_12_ 3 A 14 1 1 1 TFF * R 2 AB-------------- cnt_13_ 4 A 15 1 1 1 TFF * R 2 AB-------------- cnt_14_ 5 A 16 1 1 1 TFF * R 2 AB-------------- cnt_15_ 6 A 17 1 1 1 TFF * R 2 AB-------------- cnt_16_ 7 A 18 1 1 1 TFF * R 2 AB-------------- cnt_17_ 8 A 19 1 1 1 TFF * R 2 AB-------------- cnt_18_ 9 A 20 1 1 1 TFF * R 2 AB-------------- cnt_19_ 1 B 3 1 2 1 DFF * R 3 ABC------------- cnt_1_ 10 A 21 1 1 1 TFF * R 2 AB-------------- cnt_20_ 11 A 22 1 1 1 TFF * R 2 AB-------------- cnt_21_ 12 A 23 1 1 1 TFF * R 2 AB-------------- cnt_22_ 12 B 24 1 1 1 TFF * R 4 AB----------MN-- cnt_23_ 2 B 25 1 1 1 TFF * R 3 A-----------MN-- cnt_24_ 0 A 27 1 2 1 DFF * R 3 A-----------MN-- cnt_25_ 3 M 6 2 2 1 DFF * R 2 ------------MN-- cnt_26_ 5 M 6 2 1 1 TFF * R 2 ------------MN-- cnt_27_ 7 M 7 2 1 1 TFF * R 2 ------------MN-- cnt_28_ 9 M 8 2 1 1 TFF * R 1 -------------N-- cnt_29_ 5 C 4 1 3 1 DFF * R 3 ABC------------- cnt_2_ 3 N 9 2 1 1 TFF * R 1 -------------N-- cnt_30_ 4 N 10 2 1 1 TFF * R 1 -------------N-- cnt_31_ 5 N 11 2 1 1 TFF * R 2 ------------MN-- cnt_32_ 6 N 12 2 1 1 TFF * R 1 -------------N-- cnt_33_ 7 N 13 2 1 1 TFF * R 1 -------------N-- cnt_34_ 8 N 14 2 1 1 TFF * R 1 -------------N-- cnt_35_ 9 N 15 2 1 1 TFF * R 2 ------------MN-- cnt_36_ 10 N 16 2 1 1 TFF * R 1 -------------N-- cnt_37_ 11 N 17 2 1 1 TFF * R 1 -------------N-- cnt_38_ 12 N 18 2 1 1 TFF * R 1 -------------N-- cnt_39_ 2 C 5 1 4 1 DFF * R 3 ABC------------- cnt_3_ 0 B 6 1 2 1 DFF * R 2 AB-------------- cnt_4_ 3 B 6 1 1 1 TFF * R 2 AB-------------- cnt_5_ 4 B 7 1 1 1 TFF * R 2 AB-------------- cnt_6_ 5 B 8 1 1 1 TFF * R 2 AB-------------- cnt_7_ 6 B 9 1 1 1 TFF * R 2 AB-------------- cnt_8_ 7 B 10 1 1 1 TFF * R 2 AB-------------- cnt_9_ 5 L 2 1 1 1 DFF * R 3 --------I-KL---- u_led_7_seg_cnt_0_ 7 K 11 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_10_ 8 K 12 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_11_ 9 K 13 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_12_ 10 K 14 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_13_ 11 K 15 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_14_ 12 K 16 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_15_ 11 L 17 1 1 1 TFF * R 1 ----------K----- u_led_7_seg_cnt_16_ 13 K 18 1 1 1 TFF * R 1 ----------K----- u_led_7_seg_cnt_17_ 1 K 19 1 1 1 TFF * R 3 ----------K-MN-- u_led_7_seg_cnt_18_ 2 K 20 1 1 1 TFF * R 2 ------------MN-- u_led_7_seg_cnt_19_ 5 I 3 1 2 1 DFF * R 3 --------I-KL---- u_led_7_seg_cnt_1_ 13 N 2 1 1 1 DFF * R 2 --------IJ------ u_led_7_seg_cnt_1d_18_ 12 M 2 1 1 1 DFF * R 2 --------IJ------ u_led_7_seg_cnt_1d_19_ 3 L 4 1 3 1 DFF * R 2 ----------KL---- u_led_7_seg_cnt_2_ 1 L 5 1 4 1 DFF * R 2 ----------KL---- u_led_7_seg_cnt_3_ 0 K 6 1 2 1 DFF * R 2 ----------KL---- u_led_7_seg_cnt_4_ 7 L 6 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_5_ 3 K 7 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_6_ 4 K 8 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_7_ 5 K 9 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_8_ 6 K 10 1 1 1 TFF * R 2 ----------KL---- u_led_7_seg_cnt_9_ 1 M 7 1 4 1 DFF * R 4 ------GHIJ------ u_led_7_seg_disp_data_r_0_ 0 N 7 1 4 1 DFF * R 4 ------GHIJ------ u_led_7_seg_disp_data_r_1_ 1 N 7 1 4 1 DFF * R 4 ------GHIJ------ u_led_7_seg_disp_data_r_2_ 2 N 7 1 4 1 DFF * R 4 ------GHIJ------ u_led_7_seg_disp_data_r_3_ ----------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
N_48 = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q ; (1 pterm, 23 signals) cnt_0_.D = !cnt_0_.Q ; (1 pterm, 1 signal) cnt_0_.C = clk ; (1 pterm, 1 signal) cnt_0_.AR = !reset_n ; (1 pterm, 1 signal) cnt_10_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q ; (1 pterm, 10 signals) cnt_10_.C = clk ; (1 pterm, 1 signal) cnt_10_.AR = !reset_n ; (1 pterm, 1 signal) cnt_11_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q ; (1 pterm, 11 signals) cnt_11_.C = clk ; (1 pterm, 1 signal) cnt_11_.AR = !reset_n ; (1 pterm, 1 signal) cnt_12_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q ; (1 pterm, 12 signals) cnt_12_.C = clk ; (1 pterm, 1 signal) cnt_12_.AR = !reset_n ; (1 pterm, 1 signal) cnt_13_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q ; (1 pterm, 13 signals) cnt_13_.C = clk ; (1 pterm, 1 signal) cnt_13_.AR = !reset_n ; (1 pterm, 1 signal) cnt_14_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q ; (1 pterm, 14 signals) cnt_14_.C = clk ; (1 pterm, 1 signal) cnt_14_.AR = !reset_n ; (1 pterm, 1 signal) cnt_15_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q ; (1 pterm, 15 signals) cnt_15_.C = clk ; (1 pterm, 1 signal) cnt_15_.AR = !reset_n ; (1 pterm, 1 signal) cnt_16_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q ; (1 pterm, 16 signals) cnt_16_.C = clk ; (1 pterm, 1 signal) cnt_16_.AR = !reset_n ; (1 pterm, 1 signal) cnt_17_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q ; (1 pterm, 17 signals) cnt_17_.C = clk ; (1 pterm, 1 signal) cnt_17_.AR = !reset_n ; (1 pterm, 1 signal) cnt_18_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q ; (1 pterm, 18 signals) cnt_18_.C = clk ; (1 pterm, 1 signal) cnt_18_.AR = !reset_n ; (1 pterm, 1 signal) cnt_19_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q ; (1 pterm, 19 signals) cnt_19_.C = clk ; (1 pterm, 1 signal) cnt_19_.AR = !reset_n ; (1 pterm, 1 signal) cnt_1_.D = cnt_0_.Q & !cnt_1_.Q # !cnt_0_.Q & cnt_1_.Q ; (2 pterms, 2 signals) cnt_1_.C = clk ; (1 pterm, 1 signal) cnt_1_.AR = !reset_n ; (1 pterm, 1 signal) cnt_20_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q ; (1 pterm, 20 signals) cnt_20_.C = clk ; (1 pterm, 1 signal) cnt_20_.AR = !reset_n ; (1 pterm, 1 signal) cnt_21_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q ; (1 pterm, 21 signals) cnt_21_.C = clk ; (1 pterm, 1 signal) cnt_21_.AR = !reset_n ; (1 pterm, 1 signal) cnt_22_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q ; (1 pterm, 22 signals) cnt_22_.C = clk ; (1 pterm, 1 signal) cnt_22_.AR = !reset_n ; (1 pterm, 1 signal) cnt_23_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q ; (1 pterm, 23 signals) cnt_23_.C = clk ; (1 pterm, 1 signal) cnt_23_.AR = !reset_n ; (1 pterm, 1 signal) cnt_24_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q ; (1 pterm, 24 signals) cnt_24_.C = clk ; (1 pterm, 1 signal) cnt_24_.AR = !reset_n ; (1 pterm, 1 signal) cnt_25_.D.X1 = cnt_25_.Q ; (1 pterm, 1 signal) cnt_25_.D.X2 = cnt_24_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_16_.Q & cnt_17_.Q & cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q ; (1 pterm, 25 signals) cnt_25_.C = clk ; (1 pterm, 1 signal) cnt_25_.AR = !reset_n ; (1 pterm, 1 signal) cnt_26_.D.X1 = cnt_26_.Q ; (1 pterm, 1 signal) cnt_26_.D.X2 = cnt_24_.Q & cnt_25_.Q & cnt_23_.Q & N_48 ; (1 pterm, 4 signals) cnt_26_.C = clk ; (1 pterm, 1 signal) cnt_26_.AR = !reset_n ; (1 pterm, 1 signal) cnt_27_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_23_.Q & N_48 ; (1 pterm, 5 signals) cnt_27_.C = clk ; (1 pterm, 1 signal) cnt_27_.AR = !reset_n ; (1 pterm, 1 signal) cnt_28_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_23_.Q & N_48 ; (1 pterm, 6 signals) cnt_28_.C = clk ; (1 pterm, 1 signal) cnt_28_.AR = !reset_n ; (1 pterm, 1 signal) cnt_29_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_23_.Q & N_48 ; (1 pterm, 7 signals) cnt_29_.C = clk ; (1 pterm, 1 signal) cnt_29_.AR = !reset_n ; (1 pterm, 1 signal) cnt_2_.D = cnt_0_.Q & cnt_1_.Q & !cnt_2_.Q # !cnt_1_.Q & cnt_2_.Q # !cnt_0_.Q & cnt_2_.Q ; (3 pterms, 3 signals) cnt_2_.C = clk ; (1 pterm, 1 signal) cnt_2_.AR = !reset_n ; (1 pterm, 1 signal) cnt_30_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_23_.Q & N_48 ; (1 pterm, 8 signals) cnt_30_.C = clk ; (1 pterm, 1 signal) cnt_30_.AR = !reset_n ; (1 pterm, 1 signal) cnt_31_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_23_.Q & N_48 ; (1 pterm, 9 signals) cnt_31_.C = clk ; (1 pterm, 1 signal) cnt_31_.AR = !reset_n ; (1 pterm, 1 signal) cnt_32_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_23_.Q & N_48 ; (1 pterm, 10 signals) cnt_32_.C = clk ; (1 pterm, 1 signal) cnt_32_.AR = !reset_n ; (1 pterm, 1 signal) cnt_33_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_23_.Q & N_48 ; (1 pterm, 11 signals) cnt_33_.C = clk ; (1 pterm, 1 signal) cnt_33_.AR = !reset_n ; (1 pterm, 1 signal) cnt_34_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_23_.Q & N_48 ; (1 pterm, 12 signals) cnt_34_.C = clk ; (1 pterm, 1 signal) cnt_34_.AR = !reset_n ; (1 pterm, 1 signal) cnt_35_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_34_.Q & cnt_23_.Q & N_48 ; (1 pterm, 13 signals) cnt_35_.C = clk ; (1 pterm, 1 signal) cnt_35_.AR = !reset_n ; (1 pterm, 1 signal) cnt_36_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_34_.Q & cnt_35_.Q & cnt_23_.Q & N_48 ; (1 pterm, 14 signals) cnt_36_.C = clk ; (1 pterm, 1 signal) cnt_36_.AR = !reset_n ; (1 pterm, 1 signal) cnt_37_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_34_.Q & cnt_35_.Q & cnt_36_.Q & cnt_23_.Q & N_48 ; (1 pterm, 15 signals) cnt_37_.C = clk ; (1 pterm, 1 signal) cnt_37_.AR = !reset_n ; (1 pterm, 1 signal) cnt_38_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_34_.Q & cnt_35_.Q & cnt_36_.Q & cnt_37_.Q & cnt_23_.Q & N_48 ; (1 pterm, 16 signals) cnt_38_.C = clk ; (1 pterm, 1 signal) cnt_38_.AR = !reset_n ; (1 pterm, 1 signal) cnt_39_.T = cnt_24_.Q & cnt_25_.Q & cnt_26_.Q & cnt_27_.Q & cnt_28_.Q & cnt_29_.Q & cnt_30_.Q & cnt_31_.Q & cnt_32_.Q & cnt_33_.Q & cnt_34_.Q & cnt_35_.Q & cnt_36_.Q & cnt_37_.Q & cnt_38_.Q & cnt_23_.Q & N_48 ; (1 pterm, 17 signals) cnt_39_.C = clk ; (1 pterm, 1 signal) cnt_39_.AR = !reset_n ; (1 pterm, 1 signal) cnt_3_.D = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & !cnt_3_.Q # !cnt_2_.Q & cnt_3_.Q # !cnt_1_.Q & cnt_3_.Q # !cnt_0_.Q & cnt_3_.Q ; (4 pterms, 4 signals) cnt_3_.C = clk ; (1 pterm, 1 signal) cnt_3_.AR = !reset_n ; (1 pterm, 1 signal) cnt_4_.D.X1 = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q ; (1 pterm, 4 signals) cnt_4_.D.X2 = cnt_4_.Q ; (1 pterm, 1 signal) cnt_4_.C = clk ; (1 pterm, 1 signal) cnt_4_.AR = !reset_n ; (1 pterm, 1 signal) cnt_5_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q ; (1 pterm, 5 signals) cnt_5_.C = clk ; (1 pterm, 1 signal) cnt_5_.AR = !reset_n ; (1 pterm, 1 signal) cnt_6_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q ; (1 pterm, 6 signals) cnt_6_.C = clk ; (1 pterm, 1 signal) cnt_6_.AR = !reset_n ; (1 pterm, 1 signal) cnt_7_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 7 signals) cnt_7_.C = clk ; (1 pterm, 1 signal) cnt_7_.AR = !reset_n ; (1 pterm, 1 signal) cnt_8_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q ; (1 pterm, 8 signals) cnt_8_.C = clk ; (1 pterm, 1 signal) cnt_8_.AR = !reset_n ; (1 pterm, 1 signal) cnt_9_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_7_.Q & cnt_8_.Q ; (1 pterm, 9 signals) cnt_9_.C = clk ; (1 pterm, 1 signal) cnt_9_.AR = !reset_n ; (1 pterm, 1 signal) dig_0_.D = !( !u_led_7_seg_cnt_1d_18_.Q & !u_led_7_seg_cnt_1d_19_.Q ) ; (1 pterm, 2 signals) dig_0_.C = clk ; (1 pterm, 1 signal) dig_0_.AP = !reset_n ; (1 pterm, 1 signal) dig_1_.D = !( u_led_7_seg_cnt_1d_18_.Q & !u_led_7_seg_cnt_1d_19_.Q ) ; (1 pterm, 2 signals) dig_1_.C = clk ; (1 pterm, 1 signal) dig_1_.AP = !reset_n ; (1 pterm, 1 signal) dig_2_.D = !( !u_led_7_seg_cnt_1d_18_.Q & u_led_7_seg_cnt_1d_19_.Q ) ; (1 pterm, 2 signals) dig_2_.C = clk ; (1 pterm, 1 signal) dig_2_.AP = !reset_n ; (1 pterm, 1 signal) dig_3_.D = !( u_led_7_seg_cnt_1d_18_.Q & u_led_7_seg_cnt_1d_19_.Q ) ; (1 pterm, 2 signals) dig_3_.C = clk ; (1 pterm, 1 signal) dig_3_.AP = !reset_n ; (1 pterm, 1 signal) seg_0_.D = !u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q ; (4 pterms, 4 signals) seg_0_.C = clk ; (1 pterm, 1 signal) seg_0_.AR = !reset_n ; (1 pterm, 1 signal) seg_1_.D = u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q # u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q ; (4 pterms, 4 signals) seg_1_.C = clk ; (1 pterm, 1 signal) seg_1_.AR = !reset_n ; (1 pterm, 1 signal) seg_2_.D = !u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q ; (3 pterms, 4 signals) seg_2_.C = clk ; (1 pterm, 1 signal) seg_2_.AR = !reset_n ; (1 pterm, 1 signal) seg_3_.D = !u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q ; (4 pterms, 4 signals) seg_3_.C = clk ; (1 pterm, 1 signal) seg_3_.AR = !reset_n ; (1 pterm, 1 signal) seg_4_.D = u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q # !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_3_.Q ; (3 pterms, 4 signals) seg_4_.C = clk ; (1 pterm, 1 signal) seg_4_.AR = !reset_n ; (1 pterm, 1 signal) seg_5_.D = u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_3_.Q ; (4 pterms, 4 signals) seg_5_.C = clk ; (1 pterm, 1 signal) seg_5_.AR = !reset_n ; (1 pterm, 1 signal) seg_6_.D = u_led_7_seg_disp_data_r_0_.Q & u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_0_.Q & !u_led_7_seg_disp_data_r_1_.Q & u_led_7_seg_disp_data_r_2_.Q & u_led_7_seg_disp_data_r_3_.Q # !u_led_7_seg_disp_data_r_1_.Q & !u_led_7_seg_disp_data_r_2_.Q & !u_led_7_seg_disp_data_r_3_.Q ; (3 pterms, 4 signals) seg_6_.C = clk ; (1 pterm, 1 signal) seg_6_.AR = !reset_n ; (1 pterm, 1 signal) seg_7_.D = 1 ; (1 pterm, 0 signal) seg_7_.C = clk ; (1 pterm, 1 signal) seg_7_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_0_.D = !u_led_7_seg_cnt_0_.Q ; (1 pterm, 1 signal) u_led_7_seg_cnt_0_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_0_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_10_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q ; (1 pterm, 10 signals) u_led_7_seg_cnt_10_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_10_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_11_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q ; (1 pterm, 11 signals) u_led_7_seg_cnt_11_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_11_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_12_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q ; (1 pterm, 12 signals) u_led_7_seg_cnt_12_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_12_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_13_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q ; (1 pterm, 13 signals) u_led_7_seg_cnt_13_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_13_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_14_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q ; (1 pterm, 14 signals) u_led_7_seg_cnt_14_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_14_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_15_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q & u_led_7_seg_cnt_14_.Q ; (1 pterm, 15 signals) u_led_7_seg_cnt_15_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_15_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_16_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q & u_led_7_seg_cnt_14_.Q & u_led_7_seg_cnt_15_.Q ; (1 pterm, 16 signals) u_led_7_seg_cnt_16_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_16_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_17_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q & u_led_7_seg_cnt_14_.Q & u_led_7_seg_cnt_15_.Q & u_led_7_seg_cnt_16_.Q ; (1 pterm, 17 signals) u_led_7_seg_cnt_17_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_17_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_18_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q & u_led_7_seg_cnt_14_.Q & u_led_7_seg_cnt_15_.Q & u_led_7_seg_cnt_16_.Q & u_led_7_seg_cnt_17_.Q ; (1 pterm, 18 signals) u_led_7_seg_cnt_18_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_18_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_19_.T = u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q & u_led_7_seg_cnt_9_.Q & u_led_7_seg_cnt_10_.Q & u_led_7_seg_cnt_11_.Q & u_led_7_seg_cnt_12_.Q & u_led_7_seg_cnt_13_.Q & u_led_7_seg_cnt_14_.Q & u_led_7_seg_cnt_15_.Q & u_led_7_seg_cnt_16_.Q & u_led_7_seg_cnt_17_.Q ; (1 pterm, 19 signals) u_led_7_seg_cnt_19_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_19_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_1_.D = u_led_7_seg_cnt_0_.Q & !u_led_7_seg_cnt_1_.Q # !u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q ; (2 pterms, 2 signals) u_led_7_seg_cnt_1_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_1_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_18_.D = u_led_7_seg_cnt_18_.Q ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_18_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_18_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_19_.D = u_led_7_seg_cnt_19_.Q ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_19_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_1d_19_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_2_.D = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & !u_led_7_seg_cnt_2_.Q # !u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q # !u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_2_.Q ; (3 pterms, 3 signals) u_led_7_seg_cnt_2_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_2_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_3_.D = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & !u_led_7_seg_cnt_3_.Q # !u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q # !u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_3_.Q # !u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_3_.Q ; (4 pterms, 4 signals) u_led_7_seg_cnt_3_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_3_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_4_.D.X1 = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q ; (1 pterm, 4 signals) u_led_7_seg_cnt_4_.D.X2 = u_led_7_seg_cnt_4_.Q ; (1 pterm, 1 signal) u_led_7_seg_cnt_4_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_4_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_5_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q ; (1 pterm, 5 signals) u_led_7_seg_cnt_5_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_5_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_6_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q ; (1 pterm, 6 signals) u_led_7_seg_cnt_6_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_6_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_7_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q ; (1 pterm, 7 signals) u_led_7_seg_cnt_7_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_7_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_8_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q ; (1 pterm, 8 signals) u_led_7_seg_cnt_8_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_8_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_cnt_9_.T = u_led_7_seg_cnt_0_.Q & u_led_7_seg_cnt_1_.Q & u_led_7_seg_cnt_2_.Q & u_led_7_seg_cnt_3_.Q & u_led_7_seg_cnt_4_.Q & u_led_7_seg_cnt_5_.Q & u_led_7_seg_cnt_6_.Q & u_led_7_seg_cnt_7_.Q & u_led_7_seg_cnt_8_.Q ; (1 pterm, 9 signals) u_led_7_seg_cnt_9_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_cnt_9_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_0_.D = cnt_24_.Q & !u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_28_.Q & u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_32_.Q & !u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q # cnt_36_.Q & u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q ; (4 pterms, 6 signals) u_led_7_seg_disp_data_r_0_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_0_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_1_.D = cnt_25_.Q & !u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_29_.Q & u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_33_.Q & !u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q # cnt_37_.Q & u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q ; (4 pterms, 6 signals) u_led_7_seg_disp_data_r_1_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_1_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_2_.D = cnt_26_.Q & !u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_30_.Q & u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_34_.Q & !u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q # cnt_38_.Q & u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q ; (4 pterms, 6 signals) u_led_7_seg_disp_data_r_2_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_2_.AR = !reset_n ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_3_.D = cnt_27_.Q & !u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_31_.Q & u_led_7_seg_cnt_18_.Q & !u_led_7_seg_cnt_19_.Q # cnt_35_.Q & !u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q # cnt_39_.Q & u_led_7_seg_cnt_18_.Q & u_led_7_seg_cnt_19_.Q ; (4 pterms, 6 signals) u_led_7_seg_disp_data_r_3_.C = clk ; (1 pterm, 1 signal) u_led_7_seg_disp_data_r_3_.AR = !reset_n ; (1 pterm, 1 signal)