********** Mapped Logic ********** |
N_PZ_299 <= (NOT x_cnt(8) AND NOT x_cnt(9)); |
FTCPE_valid: FTCPE port map (valid,valid_T,clk,NOT reset_n,'0','1');
valid_T <= ((x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND N_PZ_299 AND NOT valid AND valid_y) OR (x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND NOT x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND valid AND valid_y)); |
FTCPE_valid_y: FTCPE port map (valid_y,valid_y_T,clk,NOT reset_n,'0','1');
valid_y_T <= ((valid_y AND y_cnt(0) AND NOT y_cnt(1) AND y_cnt(2) AND NOT y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(9) AND NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)) OR (NOT valid_y AND y_cnt(0) AND NOT y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))); |
FDCPE_vga_b: FDCPE port map (vga_b,vga_b_D,clk,NOT reset_n,'0','1');
vga_b_D <= ((x_dis(10) AND valid AND vga_b) OR (x_dis(11) AND valid AND vga_b) OR (x_dis(9) AND valid AND x_dis(8) AND vga_b) OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid) OR (x_dis(6) AND x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8)) OR (NOT x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4)) OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(3)) OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(2)) OR (x_dis(5) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8)) OR (NOT x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(4) AND NOT x_dis(8)) OR (NOT x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8) AND NOT x_dis(3)) OR (NOT x_dis(5) AND NOT x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(4)) OR (x_dis(5) AND x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8) AND x_dis(3)) OR (x_dis(5) AND x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8) AND x_dis(2)) OR (x_dis(5) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8) AND x_dis(3) AND x_dis(2)) OR (NOT x_dis(5) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(4) AND NOT x_dis(8) AND NOT x_dis(3)) OR (x_dis(5) AND NOT x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND NOT x_dis(8) AND x_dis(3) AND x_dis(2))); |
FDCPE_vga_g: FDCPE port map (vga_g,vga_g_D,clk,NOT reset_n,'0','1');
vga_g_D <= ((x_dis(10) AND valid AND vga_g) OR (x_dis(11) AND valid AND vga_g) OR (x_dis(9) AND valid AND x_dis(8) AND vga_g) OR (x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8)) OR (x_dis(5) AND x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8)) OR (x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND NOT x_dis(8)) OR (x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8) AND x_dis(3)) OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(4) AND x_dis(8)) OR (x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND NOT x_dis(8) AND x_dis(3))); |
FTCPE_vga_hsync: FTCPE port map (vga_hsync,vga_hsync_T,clk,'0',NOT reset_n,'1');
vga_hsync_T <= ((x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT vga_hsync) OR (NOT x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND vga_hsync)); |
FDCPE_vga_r: FDCPE port map (vga_r,vga_r_D,clk,NOT reset_n,'0','1');
vga_r_D <= ((x_dis(9) AND valid AND vga_r) OR (x_dis(10) AND valid AND vga_r) OR (x_dis(11) AND valid AND vga_r) OR (x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(8)) OR (x_dis(5) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8)) OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid) OR (x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(8)) OR (x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8))); |
FTCPE_vga_vsync: FTCPE port map (vga_vsync,vga_vsync_T,clk,'0',NOT reset_n,'1');
vga_vsync_T <= ((NOT y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND NOT y_cnt(3) AND NOT y_cnt(5) AND NOT y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11) AND NOT vga_vsync) OR (NOT y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND NOT y_cnt(3) AND NOT y_cnt(5) AND NOT y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11) AND vga_vsync)); |
FTCPE_x_cnt0: FTCPE port map (x_cnt(0),'0',clk,NOT reset_n,'0','1'); |
FTCPE_x_cnt1: FTCPE port map (x_cnt(1),x_cnt(0),clk,NOT reset_n,'0','1'); |
FTCPE_x_cnt2: FTCPE port map (x_cnt(2),x_cnt_T(2),clk,NOT reset_n,'0','1');
x_cnt_T(2) <= (x_cnt(0) AND x_cnt(1)); |
FTCPE_x_cnt3: FTCPE port map (x_cnt(3),x_cnt_T(3),clk,NOT reset_n,'0','1');
x_cnt_T(3) <= (x_cnt(0) AND x_cnt(2) AND x_cnt(1)); |
FTCPE_x_cnt4: FTCPE port map (x_cnt(4),x_cnt_T(4),clk,NOT reset_n,'0','1');
x_cnt_T(4) <= NOT (((NOT x_cnt(3)) OR (NOT x_cnt(0)) OR (NOT x_cnt(2)) OR (NOT x_cnt(1)) OR (NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11)))); |
FTCPE_x_cnt5: FTCPE port map (x_cnt(5),x_cnt_T(5),clk,NOT reset_n,'0','1');
x_cnt_T(5) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(4)); |
FTCPE_x_cnt6: FTCPE port map (x_cnt(6),x_cnt_T(6),clk,NOT reset_n,'0','1');
x_cnt_T(6) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4)); |
FTCPE_x_cnt7: FTCPE port map (x_cnt(7),x_cnt_T(7),clk,NOT reset_n,'0','1');
x_cnt_T(7) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6)); |
FTCPE_x_cnt8: FTCPE port map (x_cnt(8),x_cnt_T(8),clk,NOT reset_n,'0','1');
x_cnt_T(8) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(7)); |
FTCPE_x_cnt9: FTCPE port map (x_cnt(9),x_cnt_T(9),clk,NOT reset_n,'0','1');
x_cnt_T(9) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7)); |
FTCPE_x_cnt10: FTCPE port map (x_cnt(10),x_cnt_T(10),clk,NOT reset_n,'0','1');
x_cnt_T(10) <= ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11))); |
FTCPE_x_cnt11: FTCPE port map (x_cnt(11),x_cnt_T(11),clk,NOT reset_n,'0','1');
x_cnt_T(11) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9) AND x_cnt(10)); |
FDCPE_x_dis2: FDCPE port map (x_dis(2),x_dis_D(2),clk,NOT reset_n,'0','1');
x_dis_D(2) <= ((x_cnt(2) AND NOT x_cnt(6) AND x_cnt(8) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(2) AND x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(2) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND x_cnt(2) AND NOT x_cnt(5) AND x_cnt(8) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(2) AND NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(8) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(2) AND x_cnt(6) AND x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(3) AND x_cnt(2) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11))); |
FDCPE_x_dis3: FDCPE port map (x_dis(3),x_dis_D(3),clk,NOT reset_n,'0','1');
x_dis_D(3) <= (NOT x_cnt(3) AND NOT x_cnt(10) AND NOT x_cnt(11)) XOR ((NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11))); |
FDCPE_x_dis4: FDCPE port map (x_dis(4),x_dis_D(4),clk,NOT reset_n,'0','1');
x_dis_D(4) <= NOT (((x_cnt(10)) OR (x_cnt(11)) OR (x_cnt(3) AND x_cnt(4)) OR (NOT x_cnt(3) AND NOT x_cnt(4)) OR (NOT x_cnt(6) AND N_PZ_299) OR (NOT x_cnt(7) AND N_PZ_299) OR (x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9)))); |
FDCPE_x_dis5: FDCPE port map (x_dis(5),x_dis_D(5),clk,NOT reset_n,'0','1');
x_dis_D(5) <= NOT (((x_cnt(10)) OR (x_cnt(11)) OR (NOT x_cnt(3) AND NOT x_cnt(5)) OR (NOT x_cnt(5) AND NOT x_cnt(4)) OR (NOT x_cnt(6) AND N_PZ_299) OR (NOT x_cnt(7) AND N_PZ_299) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4)) OR (x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9)))); |
FDCPE_x_dis6: FDCPE port map (x_dis(6),x_dis_D(6),clk,NOT reset_n,'0','1');
x_dis_D(6) <= ((NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (NOT x_cnt(5) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11))); |
FDCPE_x_dis7: FDCPE port map (x_dis(7),x_dis_D(7),clk,NOT reset_n,'0','1');
x_dis_D(7) <= ((x_cnt(6) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (NOT x_cnt(3) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (NOT x_cnt(5) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (NOT x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299)); |
FDCPE_x_dis8: FDCPE port map (x_dis(8),x_dis_D(8),clk,NOT reset_n,'0','1');
x_dis_D(8) <= ((NOT x_cnt(8) AND NOT x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(5) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND NOT x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11))); |
FDCPE_x_dis9: FDCPE port map (x_dis(9),x_dis_D(9),clk,NOT reset_n,'0','1');
x_dis_D(9) <= ((NOT x_cnt(6) AND x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(8) AND NOT x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(3) AND NOT x_cnt(5) AND x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(6) AND NOT x_cnt(8) AND x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)) OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11))); |
FDCPE_x_dis10: FDCPE port map (x_dis(10),'0',clk,NOT reset_n,'0','1'); |
FDCPE_x_dis11: FDCPE port map (x_dis(11),'0',clk,NOT reset_n,'0','1'); |
FTCPE_y_cnt0: FTCPE port map (y_cnt(0),y_cnt_T(0),clk,NOT reset_n,'0','1');
y_cnt_T(0) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11)); |
FTCPE_y_cnt1: FTCPE port map (y_cnt(1),y_cnt_T(1),clk,NOT reset_n,'0','1');
y_cnt_T(1) <= ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(2)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(3)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(5)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(4)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(6)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(9)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(7)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(10)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(8)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(11))); |
FTCPE_y_cnt2: FTCPE port map (y_cnt(2),y_cnt_T(2),clk,NOT reset_n,'0','1');
y_cnt_T(2) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1)); |
FDCPE_y_cnt3: FDCPE port map (y_cnt(3),y_cnt_D(3),clk,NOT reset_n,'0','1');
y_cnt_D(3) <= NOT (NOT y_cnt(3) XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)))); |
FDCPE_y_cnt4: FDCPE port map (y_cnt(4),y_cnt_D(4),clk,NOT reset_n,'0','1');
y_cnt_D(4) <= NOT (NOT y_cnt(4) XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)))); |
FTCPE_y_cnt5: FTCPE port map (y_cnt(5),y_cnt_T(5),clk,NOT reset_n,'0','1');
y_cnt_T(5) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(4)); |
FTCPE_y_cnt6: FTCPE port map (y_cnt(6),y_cnt_T(6),clk,NOT reset_n,'0','1');
y_cnt_T(6) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4)); |
FDCPE_y_cnt7: FDCPE port map (y_cnt(7),y_cnt_D(7),clk,NOT reset_n,'0','1');
y_cnt_D(7) <= NOT (NOT y_cnt(7) XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)))); |
FTCPE_y_cnt8: FTCPE port map (y_cnt(8),y_cnt_T(8),clk,NOT reset_n,'0','1');
y_cnt_T(8) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(7)); |
FDCPE_y_cnt9: FDCPE port map (y_cnt(9),y_cnt_D(9),clk,NOT reset_n,'0','1');
y_cnt_D(9) <= NOT (NOT y_cnt(9) XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(7) AND y_cnt(8)) OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)))); |
FTCPE_y_cnt10: FTCPE port map (y_cnt(10),y_cnt_T(10),clk,NOT reset_n,'0','1');
y_cnt_T(10) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND y_cnt(8)); |
FTCPE_y_cnt11: FTCPE port map (y_cnt(11),y_cnt_T(11),clk,NOT reset_n,'0','1');
y_cnt_T(11) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(9) AND y_cnt(7) AND y_cnt(10) AND y_cnt(8)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |