ispLEVER Classic 1.7.00.05.28.13 Fitter Report File
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Project_Summary
Project Name : led
Project Path : J:\My_Workspace\led_flash\par_LC4128V
Project Fitted on : Sat Dec 17 21:38:30 2011
Device : M4128_64
Package : 100
GLB Input Mux Size : 19
Available Blocks : 8
Speed : -7.5
Part Number : LC4128V-75T100C
Source Format : Pure_Verilog_HDL
Project 'led' Fit Successfully!
Compilation_Times
Prefit Time 0 secs
Load Design Time 0.20 secs
Partition Time 0.05 secs
Place Time 0.01 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
Total Input Pins 2
Total Logic Functions 36
Total Output Pins 2
Total Bidir I/O Pins 0
Total Buried Nodes 34
Total Flip-Flops 29
Total D Flip-Flops 19
Total T Flip-Flops 10
Total Latches 0
Total Product Terms 240
Total Reserved Pins 0
Total Locked Pins 4
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 1
Total Unique Resets 1
Total Unique Presets 0
Fmax Logic Levels 3
Device_Resource_Summary
Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 2 2 --> 50
Input-Only Pins 6 0 6 --> 0
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 62 2 60 --> 3
Logic Functions 128 36 92 --> 28
Input Registers 64 0 64 --> 0
GLB Inputs 288 204 84 --> 70
Logical Product Terms 640 180 460 --> 28
Occupied GLBs 8 8 0 --> 100
Macrocells 128 36 92 --> 28
Control Product Terms:
GLB Clock/Clock Enables 8 1 7 --> 12
GLB Reset/Presets 8 0 8 --> 0
Macrocell Clocks 128 0 128 --> 0
Macrocell Clock Enables 128 0 128 --> 0
Macrocell Enables 128 0 128 --> 0
Macrocell Resets 128 0 128 --> 0
Macrocell Presets 128 0 128 --> 0
Global Routing Pool 220 35 185 --> 15
GRP from IFB .. 1 .. --> ..
(from input signals) .. 1 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 34 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
GLB_Resource_Summary
# of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
-------------------------------------------------------------------------------------------
GLB A 2 21 23 0/8 0 2 0 14 17 5
GLB B 0 22 22 0/8 0 2 0 14 25 6
GLB C 20 3 23 2/8 0 3 0 13 16 5
GLB D 0 22 22 0/8 0 2 0 14 24 6
-------------------------------------------------------------------------------------------
GLB E 3 27 30 0/8 0 12 0 4 27 12
GLB F 2 28 30 0/8 0 5 0 11 29 7
GLB G 4 20 24 0/8 0 2 0 14 20 5
GLB H 12 18 30 0/8 0 8 0 8 22 8
-------------------------------------------------------------------------------------------
TOTALS: 43 161 204 2/64 0 36 0 92 180 54
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 1 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode A1CA (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
-----------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 | I_O | 0 |B0 | | | |
4 | I_O | 0 |B2 | | | |
5 | I_O | 0 |B4 | | | |
6 | I_O | 0 |B6 | | | |
7 |GNDIO0 | - | | | | |
8 | I_O | 0 |B8 | | | |
9 | I_O | 0 |B10 | | | |
10 | I_O | 0 |B12 | | | |
11 | I_O | 0 |B13 | | | |
12 | IN0 | 0 | | | | |
13 |VCCIO0 | - | | | | |
14 | I_O | 0 |C14 | | | |
15 | I_O | 0 |C12 | | | |
16 | I_O | 0 |C10 | | | |
17 | I_O | 0 |C8 | | | |
18 |GNDIO0 | - | | | | |
19 | I_O | 0 |C6 | * |LVCMOS18 | Output|led_flash_0_
20 | I_O | 0 |C5 | * |LVCMOS18 | Output|led_flash_1_
21 | I_O | 0 |C4 | | | |
22 | I_O | 0 |C2 | | | |
23 | IN1 | 0 | | | | |
24 | TCK | - | | | | |
25 | VCC | - | | | | |
26 | GND | - | | | | |
27 | IN2 | 0 | | | | |
28 | I_O | 0 |D13 | | | |
29 | I_O | 0 |D12 | | | |
30 | I_O | 0 |D10 | | | |
31 | I_O | 0 |D8 | | | |
32 |GNDIO0 | - | | | | |
33 |VCCIO0 | - | | | | |
34 | I_O | 0 |D6 | | | |
35 | I_O | 0 |D4 | | | |
36 | I_O | 0 |D2 | | | |
37 | I_O | 0 |D0 | | | |
38 |INCLK1 | 0 | | | | |
39 |INCLK2 | 1 | | | | |
40 | VCC | - | | | | |
41 | I_O | 1 |E0 | | | |
42 | I_O | 1 |E2 | | | |
43 | I_O | 1 |E4 | | | |
44 | I_O | 1 |E6 | | | |
45 |VCCIO1 | - | | | | |
46 |GNDIO1 | - | | | | |
47 | I_O | 1 |E8 | | | |
48 | I_O | 1 |E10 | | | |
49 | I_O | 1 |E12 | | | |
50 | I_O | 1 |E14 | | | |
51 | GND | - | | | | |
52 | TMS | - | | | | |
53 | I_O | 1 |F0 | | | |
54 | I_O | 1 |F2 | | | |
55 | I_O | 1 |F4 | | | |
56 | I_O | 1 |F6 | | | |
57 |GNDIO1 | - | | | | |
58 | I_O | 1 |F8 | | | |
59 | I_O | 1 |F10 | | | |
60 | I_O | 1 |F12 | | | |
61 | I_O | 1 |F13 | | | |
62 | IN3 | 1 | | | | |
63 |VCCIO1 | - | | | | |
64 | I_O | 1 |G14 | | | |
65 | I_O | 1 |G12 | | | |
66 | I_O | 1 |G10 | | | |
67 | I_O | 1 |G8 | | | |
68 |GNDIO1 | - | | | | |
69 | I_O | 1 |G6 | | | |
70 | I_O | 1 |G5 | | | |
71 | I_O | 1 |G4 | | | |
72 | I_O | 1 |G2 | | | |
73 | IN4 | 1 | | | | |
74 | TDO | - | | | | |
75 | VCC | - | | | | |
76 | GND | - | | | | |
77 | IN5 | 1 | | | | |
78 | I_O | 1 |H13 | | | |
79 | I_O | 1 |H12 | | | |
80 | I_O | 1 |H10 | | | |
81 | I_O | 1 |H8 | | | |
82 |GNDIO1 | - | | | | |
83 |VCCIO1 | - | | | | |
84 | I_O | 1 |H6 | | | |
85 | I_O | 1 |H4 | | | |
86 | I_O | 1 |H2 | | | |
87 | I_O/OE| 1 |H0 | | | |
88 |INCLK3 | 1 | | * |LVCMOS18 | Input |reset_n
89 |INCLK0 | 0 | | * |LVCMOS18 | Input |clk
90 | VCC | - | | | | |
91 | I_O/OE| 0 |A0 | | | |
92 | I_O | 0 |A2 | | | |
93 | I_O | 0 |A4 | | | |
94 | I_O | 0 |A6 | | | |
95 |VCCIO0 | - | | | | |
96 |GNDIO0 | - | | | | |
97 | I_O | 0 |A8 | | | |
98 | I_O | 0 |A10 | | | |
99 | I_O | 0 |A12 | | | |
100 | I_O | 0 |A14 | | | |
-----------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
Input_Signal_List
Input
Pin Fanout
Pin GLB Type Pullup Signal
------------------------------------------
89 -- INCLK -------- Up clk
88 -- INCLK 8 ABCDEFGH Up reset_n
------------------------------------------
Output_Signal_List
I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-----------------------------------------------------------------------------
19 C 3 1 1 1 DFF * R * -------- Fast Up led_flash_0_
20 C 3 1 1 1 DFF * R * -------- Fast Up led_flash_1_
-----------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Bidir_Signal_List
I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-----------------------------------------------------------------------
-----------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Buried_Signal_List
I C P R P Node
N L Mc R E U C I F Fanout
Mc GLB P LL PTs S Type E S P E R P Signal
---------------------------------------------------------------
12 H 10 - 1 1 COM 1 ------G- N_130
10 E 14 - 1 1 COM 2 AB------ N_138
9 E 18 - 1 1 COM 3 --C--F-H N_146
7 F 22 - 1 1 COM 3 A--DE--- N_154
12 E 8 - 1 1 COM 8 ABCDEFGH N_70_i
7 E 2 1 1 1 DFF * R 3 ----EF-H cnt_0_
2 H 11 1 1 1 TFF * R 8 ABCDEFGH cnt_10_
6 E 12 1 1 1 TFF * R 8 ABCDEFGH cnt_11_
7 H 13 1 1 1 TFF * R 8 ABCDEFGH cnt_12_
3 G 22 2 14 3 DFF * R 8 ABCDEFGH cnt_13_
3 A 22 2 11 3 DFF * R 8 ABCDEFGH cnt_14_
6 B 22 2 12 3 DFF * R 8 ABCDEFGH cnt_15_
2 B 22 2 13 3 DFF * R 8 ABCDEFGH cnt_16_
9 H 18 1 1 1 TFF * R 8 ABCDEFGH cnt_17_
1 H 22 2 11 3 DFF * R 8 ABCDEFGH cnt_18_
3 F 20 1 1 1 TFF * R 8 ABCDEFGH cnt_19_
5 H 3 1 2 1 DFF * R 3 ----EF-H cnt_1_
5 F 22 2 13 3 DFF * R 8 ABCDEFGH cnt_20_
2 C 22 2 14 3 DFF * R 8 ABCDEFGH cnt_21_
7 D 22 2 11 3 DFF * R 8 ABCDEFGH cnt_22_
1 E 22 2 12 3 DFF * R 8 ABCDEFGH cnt_23_
3 D 22 2 13 3 DFF * R 8 ABCDEFGH cnt_24_
3 E 27 1 2 2 DFF * R 8 ABCDEFGH cnt_25_
7 A 22 2 6 2 TFF * R 8 ABCDEFGH cnt_26_
0 E 4 1 3 1 DFF * R 3 ----EF-H cnt_2_
0 H 5 1 4 1 DFF * R 3 ----EF-H cnt_3_
2 E 6 1 2 2 DFF * R 3 ----EF-H cnt_4_
3 H 6 1 1 1 TFF * R 3 ----EF-H cnt_5_
8 E 7 1 1 1 TFF * R 3 ----EF-H cnt_6_
4 E 8 1 1 1 TFF * R 4 ----EFGH cnt_7_
1 F 24 1 13 3 DFF * R 8 ABCDEFGH cnt_8_
5 E 10 1 1 1 TFF * R 8 ABCDEFGH cnt_9_
11 F 13 - 1 1 COM 1 ------G- led_flash8_16
7 G 22 - 6 2 COM 1 --C----- led_flash_1__0
---------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = ORP bypass used
PostFit_Equations
N_130 = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q
& cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 10 signals)
N_138 = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_0_.Q
& cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q
& cnt_12_.Q & cnt_13_.Q ; (1 pterm, 14 signals)
N_146 = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_16_.Q
& cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q
& cnt_6_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_17_.Q ; (1 pterm, 18 signals)
N_154 = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_16_.Q
& cnt_18_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q
& cnt_5_.Q & cnt_6_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_17_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q ; (1 pterm, 22 signals)
N_70_i = cnt_7_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q
& cnt_5_.Q & cnt_6_.Q ; (1 pterm, 8 signals)
cnt_0_.D = !cnt_0_.Q ; (1 pterm, 1 signal)
cnt_0_.C = clk ; (1 pterm, 1 signal)
cnt_0_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_10_.T = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q
& cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 10 signals)
cnt_10_.C = clk ; (1 pterm, 1 signal)
cnt_10_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_11_.T = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_0_.Q & cnt_1_.Q
& cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 11 signals)
cnt_11_.C = clk ; (1 pterm, 1 signal)
cnt_11_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_12_.T = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_0_.Q
& cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 12 signals)
cnt_12_.C = clk ; (1 pterm, 1 signal)
cnt_12_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_13_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & !cnt_12_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & !cnt_12_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_10_.Q & cnt_11_.Q & cnt_12_.Q & cnt_13_.Q & N_130
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# !cnt_13_.Q & !N_130
# !cnt_11_.Q & !cnt_13_.Q
# !cnt_10_.Q & !cnt_13_.Q
# !cnt_12_.Q & !cnt_13_.Q
# cnt_25_.Q & cnt_26_.Q ) ; (14 pterms, 21 signals)
cnt_13_.C = clk ; (1 pterm, 1 signal)
cnt_13_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_14_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
& !N_138
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_15_.Q & cnt_20_.Q
& cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138 & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_14_.Q & N_138
# !cnt_14_.Q & !N_138
# cnt_25_.Q & cnt_26_.Q ) ; (11 pterms, 21 signals)
cnt_14_.C = clk ; (1 pterm, 1 signal)
cnt_14_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_15_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
& !N_138
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_20_.Q
& cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138 & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_14_.Q & cnt_15_.Q & N_138
# !cnt_14_.Q & !cnt_15_.Q
# !cnt_15_.Q & !N_138
# cnt_25_.Q & cnt_26_.Q ) ; (12 pterms, 21 signals)
cnt_15_.C = clk ; (1 pterm, 1 signal)
cnt_15_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_16_.D = !( cnt_8_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
& !N_138
# cnt_9_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_10_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_11_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138
# cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_20_.Q
& cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_138 & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_16_.Q & cnt_14_.Q & cnt_15_.Q & N_138
# !cnt_16_.Q & !cnt_15_.Q
# !cnt_16_.Q & !cnt_14_.Q
# !cnt_16_.Q & !N_138
# cnt_25_.Q & cnt_26_.Q ) ; (13 pterms, 21 signals)
cnt_16_.C = clk ; (1 pterm, 1 signal)
cnt_16_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_17_.T = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_16_.Q
& cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q
& cnt_6_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q ; (1 pterm, 17 signals)
cnt_17_.C = clk ; (1 pterm, 1 signal)
cnt_17_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_18_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
& !N_146
# cnt_9_.Q & cnt_16_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_146
# cnt_10_.Q & cnt_16_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_146
# cnt_11_.Q & cnt_16_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_146
# cnt_16_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_146
# cnt_16_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q & cnt_20_.Q
& cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & !N_146 & N_70_i
# cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q & !N_146
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_18_.Q & N_146
# !cnt_18_.Q & !N_146
# cnt_25_.Q & cnt_26_.Q ) ; (11 pterms, 21 signals)
cnt_18_.C = clk ; (1 pterm, 1 signal)
cnt_18_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_19_.T = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q & cnt_16_.Q
& cnt_18_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q
& cnt_5_.Q & cnt_6_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_17_.Q ; (1 pterm, 19 signals)
cnt_19_.C = clk ; (1 pterm, 1 signal)
cnt_19_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_1_.D = cnt_0_.Q & !cnt_1_.Q
# !cnt_0_.Q & cnt_1_.Q ; (2 pterms, 2 signals)
cnt_1_.C = clk ; (1 pterm, 1 signal)
cnt_1_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_20_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & !cnt_19_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & N_146
# !cnt_20_.Q & !N_146
# !cnt_18_.Q & !cnt_20_.Q
# cnt_25_.Q & cnt_26_.Q
# !cnt_19_.Q & !cnt_20_.Q ) ; (13 pterms, 21 signals)
cnt_20_.C = clk ; (1 pterm, 1 signal)
cnt_20_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_21_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_18_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & N_146
# !cnt_21_.Q & !N_146
# !cnt_20_.Q & !cnt_21_.Q
# !cnt_19_.Q & !cnt_21_.Q
# !cnt_18_.Q & !cnt_21_.Q
# cnt_25_.Q & cnt_26_.Q ) ; (14 pterms, 21 signals)
cnt_21_.C = clk ; (1 pterm, 1 signal)
cnt_21_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_22_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q
& !N_154
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q & !N_154
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q & !N_154
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q & !N_154
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q & !N_154
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q & !N_154 & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q
& cnt_26_.Q & !N_154
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_23_.Q & cnt_26_.Q
& !N_154
# cnt_22_.Q & N_154
# !cnt_22_.Q & !N_154
# cnt_25_.Q & cnt_26_.Q ) ; (11 pterms, 21 signals)
cnt_22_.C = clk ; (1 pterm, 1 signal)
cnt_22_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_23_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q
& !N_154
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q & !N_154
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q & !N_154
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q & !N_154
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q & !N_154
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q & !N_154 & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_26_.Q & !N_154
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_26_.Q
& !N_154
# cnt_22_.Q & cnt_23_.Q & N_154
# !cnt_22_.Q & !cnt_23_.Q
# cnt_25_.Q & cnt_26_.Q
# !cnt_23_.Q & !N_154 ) ; (12 pterms, 21 signals)
cnt_23_.C = clk ; (1 pterm, 1 signal)
cnt_23_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_24_.D = !( cnt_8_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_9_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_10_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_11_.Q & cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q & N_70_i
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# cnt_24_.Q & cnt_22_.Q & cnt_23_.Q & N_154
# !cnt_24_.Q & !N_154
# !cnt_24_.Q & !cnt_23_.Q
# !cnt_24_.Q & !cnt_22_.Q
# cnt_25_.Q & cnt_26_.Q ) ; (13 pterms, 21 signals)
cnt_24_.C = clk ; (1 pterm, 1 signal)
cnt_24_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_25_.D.X1 = cnt_7_.Q & cnt_8_.Q & cnt_9_.Q & cnt_10_.Q & cnt_11_.Q
& cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q
& cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_12_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_17_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q
& cnt_22_.Q & cnt_23_.Q ; (1 pterm, 25 signals)
cnt_25_.D.X2 = cnt_25_.Q ; (1 pterm, 1 signal)
cnt_25_.C = clk ; (1 pterm, 1 signal)
cnt_25_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_26_.T.X1 = cnt_25_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_22_.Q & cnt_23_.Q & cnt_25_.Q & !cnt_26_.Q & N_154
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& !cnt_25_.Q & cnt_26_.Q
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q & cnt_21_.Q
& cnt_22_.Q & cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& !cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q ; (5 pterms, 15 signals)
cnt_26_.T.X2 = !cnt_8_.Q & !cnt_9_.Q & !cnt_10_.Q & !cnt_11_.Q & cnt_16_.Q
& cnt_18_.Q & cnt_24_.Q & !cnt_12_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & !cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q & cnt_21_.Q
& cnt_22_.Q & cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q & !N_70_i ; (1 pterm, 20 signals)
cnt_26_.C = clk ; (1 pterm, 1 signal)
cnt_26_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_2_.D = cnt_0_.Q & cnt_1_.Q & !cnt_2_.Q
# !cnt_1_.Q & cnt_2_.Q
# !cnt_0_.Q & cnt_2_.Q ; (3 pterms, 3 signals)
cnt_2_.C = clk ; (1 pterm, 1 signal)
cnt_2_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_3_.D = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & !cnt_3_.Q
# !cnt_2_.Q & cnt_3_.Q
# !cnt_1_.Q & cnt_3_.Q
# !cnt_0_.Q & cnt_3_.Q ; (4 pterms, 4 signals)
cnt_3_.C = clk ; (1 pterm, 1 signal)
cnt_3_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_4_.D.X1 = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q ; (1 pterm, 4 signals)
cnt_4_.D.X2 = cnt_4_.Q ; (1 pterm, 1 signal)
cnt_4_.C = clk ; (1 pterm, 1 signal)
cnt_4_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_5_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q ; (1 pterm, 5 signals)
cnt_5_.C = clk ; (1 pterm, 1 signal)
cnt_5_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_6_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q ; (1 pterm, 6 signals)
cnt_6_.C = clk ; (1 pterm, 1 signal)
cnt_6_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_7_.T = cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q
& cnt_6_.Q ; (1 pterm, 7 signals)
cnt_7_.C = clk ; (1 pterm, 1 signal)
cnt_7_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_8_.D = !( cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q
& cnt_15_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & cnt_26_.Q
# cnt_7_.Q & cnt_8_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q
& cnt_4_.Q & cnt_5_.Q & cnt_6_.Q
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& cnt_26_.Q
# !cnt_8_.Q & !cnt_6_.Q
# !cnt_8_.Q & !cnt_5_.Q
# !cnt_8_.Q & !cnt_4_.Q
# !cnt_8_.Q & !cnt_3_.Q
# !cnt_8_.Q & !cnt_2_.Q
# !cnt_8_.Q & !cnt_1_.Q
# !cnt_8_.Q & !cnt_0_.Q
# !cnt_7_.Q & !cnt_8_.Q
# cnt_25_.Q & cnt_26_.Q ) ; (13 pterms, 23 signals)
cnt_8_.C = clk ; (1 pterm, 1 signal)
cnt_8_.AR = !reset_n ; (1 pterm, 1 signal)
cnt_9_.T = cnt_7_.Q & cnt_8_.Q & cnt_0_.Q & cnt_1_.Q & cnt_2_.Q & cnt_3_.Q
& cnt_4_.Q & cnt_5_.Q & cnt_6_.Q ; (1 pterm, 9 signals)
cnt_9_.C = clk ; (1 pterm, 1 signal)
cnt_9_.AR = !reset_n ; (1 pterm, 1 signal)
led_flash8_16 = !cnt_16_.Q & !cnt_18_.Q & !cnt_24_.Q & cnt_0_.Q & cnt_1_.Q
& cnt_2_.Q & cnt_3_.Q & cnt_4_.Q & cnt_5_.Q & cnt_6_.Q & cnt_12_.Q
& cnt_21_.Q & cnt_22_.Q ; (1 pterm, 13 signals)
led_flash_0_.D = cnt_26_.Q ; (1 pterm, 1 signal)
led_flash_0_.C = clk ; (1 pterm, 1 signal)
led_flash_0_.CE = led_flash_1__0 ; (1 pterm, 1 signal)
led_flash_0_.AR = !reset_n ; (1 pterm, 1 signal)
led_flash_1_.D = cnt_26_.Q ; (1 pterm, 1 signal)
led_flash_1_.C = clk ; (1 pterm, 1 signal)
led_flash_1_.CE = led_flash_1__0 ; (1 pterm, 1 signal)
led_flash_1_.AR = !reset_n ; (1 pterm, 1 signal)
led_flash_1__0.X1 = cnt_25_.Q & cnt_26_.Q
# cnt_24_.Q & cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q & cnt_23_.Q
& !cnt_25_.Q & cnt_26_.Q
# cnt_18_.Q & cnt_24_.Q & cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q & cnt_21_.Q
& cnt_22_.Q & cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q
# cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & cnt_13_.Q & cnt_14_.Q & cnt_15_.Q
& !cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q & cnt_21_.Q & cnt_22_.Q
& cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q
# !cnt_7_.Q & !cnt_8_.Q & !cnt_9_.Q & !cnt_10_.Q & !cnt_11_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & cnt_17_.Q & cnt_19_.Q & cnt_20_.Q & cnt_23_.Q
& cnt_25_.Q & !cnt_26_.Q & led_flash8_16 ; (5 pterms, 20 signals)
led_flash_1__0.X2 = !cnt_8_.Q & !cnt_9_.Q & !cnt_10_.Q & !cnt_11_.Q
& cnt_16_.Q & cnt_18_.Q & cnt_24_.Q & !cnt_12_.Q & cnt_13_.Q
& cnt_14_.Q & cnt_15_.Q & !cnt_17_.Q & !cnt_19_.Q & cnt_20_.Q
& cnt_21_.Q & cnt_22_.Q & cnt_23_.Q & !cnt_25_.Q & cnt_26_.Q & !N_70_i ; (1 pterm, 20 signals)