ispLEVER Classic 1.7.00.05.28.13 Fitter Report File

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The Basic/Detailed Report Format can be selected in the dialog box Tools->Fitter Report File Format... Project_Summary
Project Name : io_test Project Path : J:\My_Workspace\io_test_LC4128V\par Project Fitted on : Sat Dec 17 21:44:07 2011 Device : M4128_64 Package : 100 GLB Input Mux Size : 19 Available Blocks : 8 Speed : -7.5 Part Number : LC4128V-75T100C Source Format : Pure_Verilog_HDL Project 'io_test' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.25 secs Partition Time 0.02 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 0 Total Logic Functions 64 Total Output Pins 64 Total Bidir I/O Pins 0 Total Buried Nodes 0 Total Flip-Flops 0 Total D Flip-Flops 0 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 32 Total Reserved Pins 0 Total Locked Pins 0 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 0 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 2 0 --> 100 I/O Pins 62 62 0 --> 100 Logic Functions 128 64 64 --> 50 Input Registers 64 0 64 --> 0 GLB Inputs 288 0 288 --> 0 Logical Product Terms 640 32 608 --> 5 Occupied GLBs 8 8 0 --> 100 Macrocells 128 64 64 --> 50 Control Product Terms: GLB Clock/Clock Enables 8 0 8 --> 0 GLB Reset/Presets 8 0 8 --> 0 Macrocell Clocks 128 0 128 --> 0 Macrocell Clock Enables 128 0 128 --> 0 Macrocell Enables 128 0 128 --> 0 Macrocell Resets 128 0 128 --> 0 Macrocell Presets 128 0 128 --> 0 Global Routing Pool 220 0 220 --> 0 GRP from IFB .. 0 .. --> .. (from input signals) .. 0 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 0 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 0 0 0 7/8 0 8 0 8 4 8 GLB B 0 0 0 8/8 0 8 0 8 3 8 GLB C 0 0 0 8/8 0 8 0 8 6 8 GLB D 0 0 0 8/8 0 8 0 8 1 8 ------------------------------------------------------------------------------------------- GLB E 0 0 0 8/8 0 8 0 8 4 8 GLB F 0 0 0 8/8 0 8 0 8 6 8 GLB G 0 0 0 8/8 0 8 0 8 5 8 GLB H 0 0 0 7/8 0 8 0 8 3 8 ------------------------------------------------------------------------------------------- TOTALS: 0 0 0 62/64 0 64 0 64 32 64 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : No Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode 7F60 (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name -------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |B0 | |LVCMOS18 | Output|io3 4 | I_O | 0 |B2 | |LVCMOS18 | Output|io30 5 | I_O | 0 |B4 | |LVCMOS18 | Output|io58 6 | I_O | 0 |B6 | |LVCMOS18 | Output|io20 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |B8 | |LVCMOS18 | Output|io81 9 | I_O | 0 |B10 | |LVCMOS18 | Output|io14 10 | I_O | 0 |B12 | |LVCMOS18 | Output|io49 11 | I_O | 0 |B13 | |LVCMOS18 | Output|io94 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |C14 | |LVCMOS18 | Output|io15 15 | I_O | 0 |C12 | |LVCMOS18 | Output|io53 16 | I_O | 0 |C10 | |LVCMOS18 | Output|io21 17 | I_O | 0 |C8 | |LVCMOS18 | Output|io98 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |C6 | |LVCMOS18 | Output|io85 20 | I_O | 0 |C5 | |LVCMOS18 | Output|io65 21 | I_O | 0 |C4 | |LVCMOS18 | Output|io35 22 | I_O | 0 |C2 | |LVCMOS18 | Output|io4 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |D13 | |LVCMOS18 | Output|io72 29 | I_O | 0 |D12 | |LVCMOS18 | Output|io36 30 | I_O | 0 |D10 | |LVCMOS18 | Output|io16 31 | I_O | 0 |D8 | |LVCMOS18 | Output|io99 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |D6 | |LVCMOS18 | Output|io91 35 | I_O | 0 |D4 | |LVCMOS18 | Output|io55 36 | I_O | 0 |D2 | |LVCMOS18 | Output|io28 37 | I_O | 0 |D0 | |LVCMOS18 | Output|io8 38 |INCLK1 | 0 | | | | | 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |E0 | |LVCMOS18 | Output|io5 42 | I_O | 1 |E2 | |LVCMOS18 | Output|io71 43 | I_O | 1 |E4 | |LVCMOS18 | Output|io17 44 | I_O | 1 |E6 | |LVCMOS18 | Output|io37 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |E8 | |LVCMOS18 | Output|io44 48 | I_O | 1 |E10 | |LVCMOS18 | Output|io66 49 | I_O | 1 |E12 | |LVCMOS18 | Output|io86 50 | I_O | 1 |E14 | |LVCMOS18 | Output|io59 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |F0 | |LVCMOS18 | Output|io41 54 | I_O | 1 |F2 | |LVCMOS18 | Output|io6 55 | I_O | 1 |F4 | |LVCMOS18 | Output|io48 56 | I_O | 1 |F6 | |LVCMOS18 | Output|io67 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |F8 | |LVCMOS18 | Output|io79 59 | I_O | 1 |F10 | |LVCMOS18 | Output|io60 60 | I_O | 1 |F12 | |LVCMOS18 | Output|io22 61 | I_O | 1 |F13 | |LVCMOS18 | Output|io87 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |G14 | |LVCMOS18 | Output|io9 65 | I_O | 1 |G12 | |LVCMOS18 | Output|io80 66 | I_O | 1 |G10 | |LVCMOS18 | Output|io69 67 | I_O | 1 |G8 | |LVCMOS18 | Output|io61 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |G6 | |LVCMOS18 | Output|io50 70 | I_O | 1 |G5 | |LVCMOS18 | Output|io42 71 | I_O | 1 |G4 | |LVCMOS18 | Output|io31 72 | I_O | 1 |G2 | |LVCMOS18 | Output|io93 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |H13 | |LVCMOS18 | Output|io70 79 | I_O | 1 |H12 | |LVCMOS18 | Output|io84 80 | I_O | 1 |H10 | |LVCMOS18 | Output|io43 81 | I_O | 1 |H8 | |LVCMOS18 | Output|io54 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |H6 | |LVCMOS18 | Output|io11 85 | I_O | 1 |H4 | |LVCMOS18 | Output|io97 86 | I_O | 1 |H2 | |LVCMOS18 | Output|io64 87 | I_O/OE| 1 |H0 | |LVCMOS18 | Output|io34 88 |INCLK3 | 1 | | | | | 89 |INCLK0 | 0 | | | | | 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A0 | |LVCMOS18 | Output|io10 92 | I_O | 0 |A2 | |LVCMOS18 | Output|io47 93 | I_O | 0 |A4 | |LVCMOS18 | Output|io100 94 | I_O | 0 |A6 | |LVCMOS18 | Output|io29 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |A8 | |LVCMOS18 | Output|io56 98 | I_O | 0 |A10 | |LVCMOS18 | Output|io19 99 | I_O | 0 |A12 | |LVCMOS18 | Output|io78 100 | I_O | 0 |A14 | |LVCMOS18 | Output|io92 -------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ----------------------------------------- ----------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ----------------------------------------------------------------------- 91 A 0 - 0 1 COM -------- Fast Up io10 93 A 0 - 1 1 COM -------- Fast Up io100 84 H 0 - 1 1 COM -------- Fast Up io11 9 B 0 - 0 1 COM -------- Fast Up io14 14 C 0 - 1 1 COM -------- Fast Up io15 30 D 0 - 0 1 COM -------- Fast Up io16 43 E 0 - 1 1 COM -------- Fast Up io17 98 A 0 - 0 1 COM -------- Fast Up io19 6 B 0 - 1 1 COM -------- Fast Up io20 16 C 0 - 0 1 COM -------- Fast Up io21 60 F 0 - 1 1 COM -------- Fast Up io22 36 D 0 - 0 1 COM -------- Fast Up io28 94 A 0 - 1 1 COM -------- Fast Up io29 3 B 0 - 0 1 COM -------- Fast Up io3 4 B 0 - 0 1 COM -------- Fast Up io30 71 G 0 - 1 1 COM -------- Fast Up io31 87 H 0 - 0 1 COM -------- Fast Up io34 21 C 0 - 1 1 COM -------- Fast Up io35 29 D 0 - 0 1 COM -------- Fast Up io36 44 E 0 - 1 1 COM -------- Fast Up io37 22 C 0 - 1 1 COM -------- Fast Up io4 53 F 0 - 0 1 COM -------- Fast Up io41 70 G 0 - 1 1 COM -------- Fast Up io42 80 H 0 - 0 1 COM -------- Fast Up io43 47 E 0 - 1 1 COM -------- Fast Up io44 92 A 0 - 0 1 COM -------- Fast Up io47 55 F 0 - 1 1 COM -------- Fast Up io48 10 B 0 - 0 1 COM -------- Fast Up io49 41 E 0 - 0 1 COM -------- Fast Up io5 69 G 0 - 1 1 COM -------- Fast Up io50 15 C 0 - 0 1 COM -------- Fast Up io53 81 H 0 - 1 1 COM -------- Fast Up io54 35 D 0 - 0 1 COM -------- Fast Up io55 97 A 0 - 1 1 COM -------- Fast Up io56 5 B 0 - 0 1 COM -------- Fast Up io58 50 E 0 - 1 1 COM -------- Fast Up io59 54 F 0 - 1 1 COM -------- Fast Up io6 59 F 0 - 0 1 COM -------- Fast Up io60 67 G 0 - 1 1 COM -------- Fast Up io61 86 H 0 - 0 1 COM -------- Fast Up io64 20 C 0 - 1 1 COM -------- Fast Up io65 48 E 0 - 0 1 COM -------- Fast Up io66 56 F 0 - 1 1 COM -------- Fast Up io67 66 G 0 - 0 1 COM -------- Fast Up io69 78 H 0 - 1 1 COM -------- Fast Up io70 42 E 0 - 0 1 COM -------- Fast Up io71 28 D 0 - 1 1 COM -------- Fast Up io72 99 A 0 - 0 1 COM -------- Fast Up io78 58 F 0 - 1 1 COM -------- Fast Up io79 37 D 0 - 0 1 COM -------- Fast Up io8 65 G 0 - 0 1 COM -------- Fast Up io80 8 B 0 - 1 1 COM -------- Fast Up io81 79 H 0 - 0 1 COM -------- Fast Up io84 19 C 0 - 1 1 COM -------- Fast Up io85 49 E 0 - 0 1 COM -------- Fast Up io86 61 F 0 - 1 1 COM -------- Fast Up io87 64 G 0 - 1 1 COM -------- Fast Up io9 34 D 0 - 0 1 COM -------- Fast Up io91 100 A 0 - 1 1 COM -------- Fast Up io92 72 G 0 - 0 1 COM -------- Fast Up io93 11 B 0 - 1 1 COM -------- Fast Up io94 85 H 0 - 0 1 COM -------- Fast Up io97 17 C 0 - 1 1 COM -------- Fast Up io98 31 D 0 - 0 1 COM -------- Fast Up io99 ----------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ----------------------------------------------------------------------- ----------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
PostFit_Equations
io10 = 0 ; (0 pterm, 0 signal) io100 = 1 ; (1 pterm, 0 signal) io11 = 1 ; (1 pterm, 0 signal) io14 = 0 ; (0 pterm, 0 signal) io15 = 1 ; (1 pterm, 0 signal) io16 = 0 ; (0 pterm, 0 signal) io17 = 1 ; (1 pterm, 0 signal) io19 = 0 ; (0 pterm, 0 signal) io20 = 1 ; (1 pterm, 0 signal) io21 = 0 ; (0 pterm, 0 signal) io22 = 1 ; (1 pterm, 0 signal) io28 = 0 ; (0 pterm, 0 signal) io29 = 1 ; (1 pterm, 0 signal) io3 = 0 ; (0 pterm, 0 signal) io30 = 0 ; (0 pterm, 0 signal) io31 = 1 ; (1 pterm, 0 signal) io34 = 0 ; (0 pterm, 0 signal) io35 = 1 ; (1 pterm, 0 signal) io36 = 0 ; (0 pterm, 0 signal) io37 = 1 ; (1 pterm, 0 signal) io4 = 1 ; (1 pterm, 0 signal) io41 = 0 ; (0 pterm, 0 signal) io42 = 1 ; (1 pterm, 0 signal) io43 = 0 ; (0 pterm, 0 signal) io44 = 1 ; (1 pterm, 0 signal) io47 = 0 ; (0 pterm, 0 signal) io48 = 1 ; (1 pterm, 0 signal) io49 = 0 ; (0 pterm, 0 signal) io5 = 0 ; (0 pterm, 0 signal) io50 = 1 ; (1 pterm, 0 signal) io53 = 0 ; (0 pterm, 0 signal) io54 = 1 ; (1 pterm, 0 signal) io55 = 0 ; (0 pterm, 0 signal) io56 = 1 ; (1 pterm, 0 signal) io58 = 0 ; (0 pterm, 0 signal) io59 = 1 ; (1 pterm, 0 signal) io6 = 1 ; (1 pterm, 0 signal) io60 = 0 ; (0 pterm, 0 signal) io61 = 1 ; (1 pterm, 0 signal) io64 = 0 ; (0 pterm, 0 signal) io65 = 1 ; (1 pterm, 0 signal) io66 = 0 ; (0 pterm, 0 signal) io67 = 1 ; (1 pterm, 0 signal) io69 = 0 ; (0 pterm, 0 signal) io70 = 1 ; (1 pterm, 0 signal) io71 = 0 ; (0 pterm, 0 signal) io72 = 1 ; (1 pterm, 0 signal) io78 = 0 ; (0 pterm, 0 signal) io79 = 1 ; (1 pterm, 0 signal) io8 = 0 ; (0 pterm, 0 signal) io80 = 0 ; (0 pterm, 0 signal) io81 = 1 ; (1 pterm, 0 signal) io84 = 0 ; (0 pterm, 0 signal) io85 = 1 ; (1 pterm, 0 signal) io86 = 0 ; (0 pterm, 0 signal) io87 = 1 ; (1 pterm, 0 signal) io9 = 1 ; (1 pterm, 0 signal) io91 = 0 ; (0 pterm, 0 signal) io92 = 1 ; (1 pterm, 0 signal) io93 = 0 ; (0 pterm, 0 signal) io94 = 1 ; (1 pterm, 0 signal) io97 = 0 ; (0 pterm, 0 signal) io98 = 1 ; (1 pterm, 0 signal) io99 = 0 ; (0 pterm, 0 signal)