cpldfit: version M.70d Xilinx Inc. Fitter Report Design Name: ps2_keypad_led_7_seg_app Date: 9-24-2013, 11:54PM Device Used: XC2C256-7-VQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 64 /256 ( 25%) 133 /896 ( 15%) 98 /640 ( 15%) 64 /256 ( 25%) 14 /80 ( 17%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 15/40 15/56 0/ 5 0/1 0/1 0/1 0/1 FB2 16/16* 38/40* 33/56 0/ 6 0/1 0/1 0/1 0/1 FB3 16/16* 25/40 54/56 0/ 4 0/1 0/1 0/1 0/1 FB4 6/16 6/40 9/56 0/ 6 0/1 0/1 0/1 0/1 FB5 0/16 0/40 0/56 0/ 2 0/1 0/1 0/1 0/1 FB6 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB7 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB8 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB9 5/16 5/40 12/56 5/ 5* 0/1 0/1 0/1 0/1 FB10 2/16 4/40 3/56 2/ 7 0/1 0/1 0/1 0/1 FB11 3/16 5/40 7/56 3/ 4 0/1 0/1 0/1 0/1 FB12 0/16 0/40 0/56 0/ 4 0/1 0/1 0/1 0/1 FB13 0/16 0/40 0/56 0/ 4 0/1 0/1 0/1 0/1 FB14 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB15 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB16 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 64/256 98/640 133/896 10/80 0/16 0/16 0/16 0/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS DGE Used/Tot Used/Tot Used/Tot Used/Tot 1/3 1/1 0/4 0/1 Signal 'clk' mapped onto global clock net GCK0. Signal 'reset_n' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 2 2 | I/O : 12 70 Output : 10 10 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 1 1 | DGE/IO : 0 1 ---- ---- Total 14 14 End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'ps2_keypad_led_7_seg_app.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. ************************* Summary of Mapped Logic ************************ ** 10 Outputs ** Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State seg<0> 3 4 2 FB9_1 78 I/O O LVCMOS18 FAST DFF RESET seg<5> 3 4 2 FB9_2 79 I/O O LVCMOS18 FAST DFF RESET dig<0> 1 1 2 FB9_4 80 I/O O LVCMOS18 FAST DFF RESET seg<3> 4 4 2 FB9_6 81 I/O O LVCMOS18 FAST DFF RESET seg<4> 3 4 2 FB9_12 82 I/O O LVCMOS18 FAST DFF RESET seg<7> 0 0 2 FB10_1 77 I/O O LVCMOS18 FAST DFF RESET seg<6> 3 4 2 FB10_2 76 I/O O LVCMOS18 FAST DFF RESET seg<2> 3 4 2 FB11_11 85 I/O O LVCMOS18 FAST DFF RESET seg<1> 3 4 2 FB11_12 86 I/O O LVCMOS18 FAST DFF RESET dig<1> 1 1 2 FB11_13 87 I/O O LVCMOS18 FAST DFF RESET ** 54 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State u_led_7_seg/cnt<10> 1 10 FB1_1 TFF RESET u_led_7_seg/cnt<9> 1 9 FB1_2 TFF RESET u_led_7_seg/cnt<15> 1 15 FB1_3 TFF RESET u_led_7_seg/cnt<8> 1 8 FB1_4 TFF RESET u_led_7_seg/cnt<7> 1 7 FB1_5 TFF RESET u_led_7_seg/cnt<14> 1 14 FB1_6 TFF RESET u_led_7_seg/cnt<6> 1 6 FB1_7 TFF RESET u_led_7_seg/cnt<5> 1 5 FB1_8 TFF RESET u_led_7_seg/cnt<4> 1 4 FB1_9 TFF RESET u_led_7_seg/cnt<3> 1 3 FB1_10 TFF RESET u_led_7_seg/cnt<2> 1 2 FB1_11 TFF RESET u_led_7_seg/cnt<13> 1 13 FB1_12 TFF RESET u_led_7_seg/cnt<12> 1 12 FB1_13 TFF RESET u_led_7_seg/cnt<11> 1 11 FB1_14 TFF RESET u_led_7_seg/cnt<1> 1 1 FB1_15 TFF RESET u_led_7_seg/cnt<0> 0 0 FB1_16 TFF RESET u_ps2scan/num_FSM_FFd9 2 3 FB2_1 DEFF RESET ps2_scan_code<1> 3 6 FB2_2 TFF RESET u_ps2scan/num_FSM_FFd10 2 3 FB2_3 DEFF RESET ps2_scan_code<0> 3 6 FB2_4 TFF RESET u_ps2scan/temp_data<0> 3 6 FB2_5 TFF RESET u_led_7_seg/disp_data_r<3> 2 3 FB2_6 DFF RESET u_led_7_seg/disp_data_r<2> 2 3 FB2_7 DFF RESET u_led_7_seg/disp_data_r<1> 2 3 FB2_8 DFF RESET u_led_7_seg/disp_data_r<0> 2 3 FB2_9 DFF RESET u_led_7_seg/cnt_1d<18> 1 1 FB2_10 DFF RESET u_led_7_seg/cnt<16> 1 16 FB2_11 TFF RESET u_ps2scan/num_FSM_FFd11 2 3 FB2_12 DEFF RESET u_led_7_seg/cnt<17> 1 17 FB2_13 TFF RESET ps2_scan_code<3> 3 6 FB2_14 TFF RESET ps2_scan_code<2> 3 6 FB2_15 TFF RESET u_led_7_seg/cnt<18> 1 18 FB2_16 TFF RESET u_ps2scan/temp_data<7> 3 6 FB3_1 TFF RESET u_ps2scan/temp_data<6> 3 6 FB3_2 TFF RESET u_ps2scan/temp_data<5> 3 6 FB3_3 TFF RESET u_ps2scan/temp_data<4> 3 6 FB3_4 TFF RESET u_ps2scan/num_FSM_FFd5 2 3 FB3_5 DEFF RESET u_ps2scan/temp_data<3> 3 6 FB3_6 TFF RESET u_ps2scan/temp_data<2> 3 6 FB3_7 TFF RESET u_ps2scan/temp_data<1> 3 6 FB3_8 TFF RESET Signal Total Total Loc Reg Reg Init Name Pts Inps Use State ps2_scan_code<7> 6 13 FB3_9 DFF RESET ps2_scan_code<6> 6 13 FB3_10 DFF RESET ps2_scan_code<5> 6 13 FB3_11 DFF RESET u_ps2scan/num_FSM_FFd4 2 3 FB3_12 DEFF RESET u_ps2scan/key_f0 4 12 FB3_13 DFF RESET u_ps2scan/num_FSM_FFd3 2 3 FB3_14 DEFF RESET ps2_scan_code<4> 6 13 FB3_15 DFF RESET u_ps2scan/num_FSM_FFd2 2 3 FB3_16 DEFF RESET u_ps2scan/ps2_clk_1d 0 0 FB4_3 DFF RESET u_ps2scan/num_FSM_FFd8 2 3 FB4_11 DEFF RESET u_ps2scan/num_FSM_FFd7 2 3 FB4_12 DEFF RESET u_ps2scan/num_FSM_FFd6 2 3 FB4_14 DEFF RESET u_ps2scan/num_FSM_FFd1 2 3 FB4_15 DEFF RESET u_ps2scan/ps2_clk_2d 1 1 FB4_16 DFF RESET ** 4 Inputs ** Signal Bank Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style reset_n 2 FB1_3 99 GSR/I/O GSR LVCMOS18 KPR ps2_clk 2 FB4_3 10 I/O I LVCMOS18 KPR ps2_data 2 FB4_5 11 I/O I LVCMOS18 KPR clk 1 FB5_6 22 GCK/I/O GCK LVCMOS18 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 15/25 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 15/41 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use u_led_7_seg/cnt<10> 1 FB1_1 (b) (b) u_led_7_seg/cnt<9> 1 FB1_2 (b) (b) u_led_7_seg/cnt<15> 1 FB1_3 99 GSR/I/O GSR u_led_7_seg/cnt<8> 1 FB1_4 (b) (b) u_led_7_seg/cnt<7> 1 FB1_5 (b) (b) u_led_7_seg/cnt<14> 1 FB1_6 97 I/O (b) u_led_7_seg/cnt<6> 1 FB1_7 (b) (b) u_led_7_seg/cnt<5> 1 FB1_8 (b) (b) u_led_7_seg/cnt<4> 1 FB1_9 (b) (b) u_led_7_seg/cnt<3> 1 FB1_10 (b) (b) u_led_7_seg/cnt<2> 1 FB1_11 (b) (b) u_led_7_seg/cnt<13> 1 FB1_12 96 I/O (b) u_led_7_seg/cnt<12> 1 FB1_13 95 I/O (b) u_led_7_seg/cnt<11> 1 FB1_14 94 I/O (b) u_led_7_seg/cnt<1> 1 FB1_15 (b) (b) u_led_7_seg/cnt<0> 0 FB1_16 (b) (b) Signals Used by Logic in Function Block 1: u_led_7_seg/cnt<0> 6: u_led_7_seg/cnt<14> 11: u_led_7_seg/cnt<5> 2: u_led_7_seg/cnt<10> 7: u_led_7_seg/cnt<1> 12: u_led_7_seg/cnt<6> 3: u_led_7_seg/cnt<11> 8: u_led_7_seg/cnt<2> 13: u_led_7_seg/cnt<7> 4: u_led_7_seg/cnt<12> 9: u_led_7_seg/cnt<3> 14: u_led_7_seg/cnt<8> 5: u_led_7_seg/cnt<13> 10: u_led_7_seg/cnt<4> 15: u_led_7_seg/cnt<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs u_led_7_seg/cnt<10> X.....XXXXXXXXX......................... 10 u_led_7_seg/cnt<9> X.....XXXXXXXX.......................... 9 u_led_7_seg/cnt<15> XXXXXXXXXXXXXXX......................... 15 u_led_7_seg/cnt<8> X.....XXXXXXX........................... 8 u_led_7_seg/cnt<7> X.....XXXXXX............................ 7 u_led_7_seg/cnt<14> XXXXX.XXXXXXXXX......................... 14 u_led_7_seg/cnt<6> X.....XXXXX............................. 6 u_led_7_seg/cnt<5> X.....XXXX.............................. 5 u_led_7_seg/cnt<4> X.....XXX............................... 4 u_led_7_seg/cnt<3> X.....XX................................ 3 u_led_7_seg/cnt<2> X.....X................................. 2 u_led_7_seg/cnt<13> XXXX..XXXXXXXXX......................... 13 u_led_7_seg/cnt<12> XXX...XXXXXXXXX......................... 12 u_led_7_seg/cnt<11> XX....XXXXXXXXX......................... 11 u_led_7_seg/cnt<1> X....................................... 1 u_led_7_seg/cnt<0> ........................................ 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 38/2 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 33/23 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use u_ps2scan/num_FSM_FFd9 2 FB2_1 1 GTS/I/O (b) ps2_scan_code<1> 3 FB2_2 (b) (b) u_ps2scan/num_FSM_FFd10 2 FB2_3 2 GTS/I/O (b) ps2_scan_code<0> 3 FB2_4 (b) (b) u_ps2scan/temp_data<0> 3 FB2_5 3 GTS/I/O (b) u_led_7_seg/disp_data_r<3> 2 FB2_6 (b) (b) u_led_7_seg/disp_data_r<2> 2 FB2_7 (b) (b) u_led_7_seg/disp_data_r<1> 2 FB2_8 (b) (b) u_led_7_seg/disp_data_r<0> 2 FB2_9 (b) (b) u_led_7_seg/cnt_1d<18> 1 FB2_10 (b) (b) u_led_7_seg/cnt<16> 1 FB2_11 (b) (b) u_ps2scan/num_FSM_FFd11 2 FB2_12 4 GTS/I/O (b) u_led_7_seg/cnt<17> 1 FB2_13 (b) (b) ps2_scan_code<3> 3 FB2_14 6 I/O (b) ps2_scan_code<2> 3 FB2_15 7 I/O (b) u_led_7_seg/cnt<18> 1 FB2_16 (b) (b) Signals Used by Logic in Function Block 1: ps2_data 14: u_led_7_seg/cnt<13> 27: u_led_7_seg/cnt<8> 2: ps2_scan_code<0> 15: u_led_7_seg/cnt<14> 28: u_led_7_seg/cnt<9> 3: ps2_scan_code<1> 16: u_led_7_seg/cnt<15> 29: u_ps2scan/key_f0 4: ps2_scan_code<2> 17: u_led_7_seg/cnt<16> 30: u_ps2scan/num_FSM_FFd1 5: ps2_scan_code<3> 18: u_led_7_seg/cnt<17> 31: u_ps2scan/num_FSM_FFd10 6: ps2_scan_code<4> 19: u_led_7_seg/cnt<18> 32: u_ps2scan/num_FSM_FFd11 7: ps2_scan_code<5> 20: u_led_7_seg/cnt<1> 33: u_ps2scan/ps2_clk_1d 8: ps2_scan_code<6> 21: u_led_7_seg/cnt<2> 34: u_ps2scan/ps2_clk_2d 9: ps2_scan_code<7> 22: u_led_7_seg/cnt<3> 35: u_ps2scan/temp_data<0> 10: u_led_7_seg/cnt<0> 23: u_led_7_seg/cnt<4> 36: u_ps2scan/temp_data<1> 11: u_led_7_seg/cnt<10> 24: u_led_7_seg/cnt<5> 37: u_ps2scan/temp_data<2> 12: u_led_7_seg/cnt<11> 25: u_led_7_seg/cnt<6> 38: u_ps2scan/temp_data<3> 13: u_led_7_seg/cnt<12> 26: u_led_7_seg/cnt<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs u_ps2scan/num_FSM_FFd9 ..............................X.XX...... 3 ps2_scan_code<1> ..X.........................XX..XX.X.... 6 u_ps2scan/num_FSM_FFd10 ...............................XXX...... 3 ps2_scan_code<0> .X..........................XX..XXX..... 6 u_ps2scan/temp_data<0> X.............................XXXXX..... 6 u_led_7_seg/disp_data_r<3> ....X...X.........X..................... 3 u_led_7_seg/disp_data_r<2> ...X...X..........X..................... 3 u_led_7_seg/disp_data_r<1> ..X...X...........X..................... 3 u_led_7_seg/disp_data_r<0> .X...X............X..................... 3 u_led_7_seg/cnt_1d<18> ..................X..................... 1 u_led_7_seg/cnt<16> .........XXXXXXX...XXXXXXXXX............ 16 u_ps2scan/num_FSM_FFd11 .............................X..XX...... 3 u_led_7_seg/cnt<17> .........XXXXXXXX..XXXXXXXXX............ 17 ps2_scan_code<3> ....X.......................XX..XX...X.. 6 ps2_scan_code<2> ...X........................XX..XX..X... 6 u_led_7_seg/cnt<18> .........XXXXXXXXX.XXXXXXXXX............ 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 25/15 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 54/2 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use u_ps2scan/temp_data<7> 3 FB3_1 (b) (b) u_ps2scan/temp_data<6> 3 FB3_2 (b) (b) u_ps2scan/temp_data<5> 3 FB3_3 (b) (b) u_ps2scan/temp_data<4> 3 FB3_4 (b) (b) u_ps2scan/num_FSM_FFd5 2 FB3_5 93 I/O (b) u_ps2scan/temp_data<3> 3 FB3_6 (b) (b) u_ps2scan/temp_data<2> 3 FB3_7 (b) (b) u_ps2scan/temp_data<1> 3 FB3_8 (b) (b) ps2_scan_code<7> 6 FB3_9 (b) (b) ps2_scan_code<6> 6 FB3_10 (b) (b) ps2_scan_code<5> 6 FB3_11 (b) (b) u_ps2scan/num_FSM_FFd4 2 FB3_12 92 I/O (b) u_ps2scan/key_f0 4 FB3_13 (b) (b) u_ps2scan/num_FSM_FFd3 2 FB3_14 91 I/O (b) ps2_scan_code<4> 6 FB3_15 (b) (b) u_ps2scan/num_FSM_FFd2 2 FB3_16 90 I/O (b) Signals Used by Logic in Function Block 1: ps2_data 10: u_ps2scan/num_FSM_FFd4 18: u_ps2scan/temp_data<0> 2: ps2_scan_code<4> 11: u_ps2scan/num_FSM_FFd5 19: u_ps2scan/temp_data<1> 3: ps2_scan_code<5> 12: u_ps2scan/num_FSM_FFd6 20: u_ps2scan/temp_data<2> 4: ps2_scan_code<6> 13: u_ps2scan/num_FSM_FFd7 21: u_ps2scan/temp_data<3> 5: ps2_scan_code<7> 14: u_ps2scan/num_FSM_FFd8 22: u_ps2scan/temp_data<4> 6: u_ps2scan/key_f0 15: u_ps2scan/num_FSM_FFd9 23: u_ps2scan/temp_data<5> 7: u_ps2scan/num_FSM_FFd1 16: u_ps2scan/ps2_clk_1d 24: u_ps2scan/temp_data<6> 8: u_ps2scan/num_FSM_FFd11 17: u_ps2scan/ps2_clk_2d 25: u_ps2scan/temp_data<7> 9: u_ps2scan/num_FSM_FFd3 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs u_ps2scan/temp_data<7> X......XX......XX.......X............... 6 u_ps2scan/temp_data<6> X......X.X.....XX......X................ 6 u_ps2scan/temp_data<5> X......X..X....XX.....X................. 6 u_ps2scan/temp_data<4> X......X...X...XX....X.................. 6 u_ps2scan/num_FSM_FFd5 ...........X...XX....................... 3 u_ps2scan/temp_data<3> X......X....X..XX...X................... 6 u_ps2scan/temp_data<2> X......X.....X.XX..X.................... 6 u_ps2scan/temp_data<1> X......X......XXX.X..................... 6 ps2_scan_code<7> ....XXX........XXXXXXXXXX............... 13 ps2_scan_code<6> ...X.XX........XXXXXXXXXX............... 13 ps2_scan_code<5> ..X..XX........XXXXXXXXXX............... 13 u_ps2scan/num_FSM_FFd4 ..........X....XX....................... 3 u_ps2scan/key_f0 .....XX........XXXXXXXXXX............... 12 u_ps2scan/num_FSM_FFd3 .........X.....XX....................... 3 ps2_scan_code<4> .X...XX........XXXXXXXXXX............... 13 u_ps2scan/num_FSM_FFd2 ........X......XX....................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 6/34 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 9/47 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB4_1 8 I/O (unused) 0 FB4_2 9 I/O u_ps2scan/ps2_clk_1d 0 FB4_3 10 I/O I (unused) 0 FB4_4 (b) (unused) 0 FB4_5 11 I/O I (unused) 0 FB4_6 12 I/O (unused) 0 FB4_7 (b) (unused) 0 FB4_8 (b) (unused) 0 FB4_9 (b) (unused) 0 FB4_10 (b) u_ps2scan/num_FSM_FFd8 2 FB4_11 (b) (b) u_ps2scan/num_FSM_FFd7 2 FB4_12 (b) (b) (unused) 0 FB4_13 13 I/O u_ps2scan/num_FSM_FFd6 2 FB4_14 (b) (b) u_ps2scan/num_FSM_FFd1 2 FB4_15 (b) (b) u_ps2scan/ps2_clk_2d 1 FB4_16 (b) (b) Signals Used by Logic in Function Block 1: u_ps2scan/num_FSM_FFd2 3: u_ps2scan/num_FSM_FFd8 5: u_ps2scan/ps2_clk_1d 2: u_ps2scan/num_FSM_FFd7 4: u_ps2scan/num_FSM_FFd9 6: u_ps2scan/ps2_clk_2d Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs u_ps2scan/num_FSM_FFd8 ...XXX.................................. 3 u_ps2scan/num_FSM_FFd7 ..X.XX.................................. 3 u_ps2scan/num_FSM_FFd6 .X..XX.................................. 3 u_ps2scan/num_FSM_FFd1 X...XX.................................. 3 u_ps2scan/ps2_clk_2d ....X................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB5_1 (b) (unused) 0 FB5_2 (b) (unused) 0 FB5_3 (b) (unused) 0 FB5_4 23 GCK/I/O (unused) 0 FB5_5 (b) (unused) 0 FB5_6 22 GCK/I/O GCK (unused) 0 FB5_7 (b) (unused) 0 FB5_8 (b) (unused) 0 FB5_9 (b) (unused) 0 FB5_10 (b) (unused) 0 FB5_11 (b) (unused) 0 FB5_12 (b) (unused) 0 FB5_13 (b) (unused) 0 FB5_14 (b) (unused) 0 FB5_15 (b) (unused) 0 FB5_16 (b) *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB6_1 (b) (unused) 0 FB6_2 24 CDR/I/O (unused) 0 FB6_3 (b) (unused) 0 FB6_4 27 GCK/I/O (unused) 0 FB6_5 (b) (unused) 0 FB6_6 (b) (unused) 0 FB6_7 (b) (unused) 0 FB6_8 (b) (unused) 0 FB6_9 (b) (unused) 0 FB6_10 (b) (unused) 0 FB6_11 (b) (unused) 0 FB6_12 28 DGE/I/O (unused) 0 FB6_13 (b) (unused) 0 FB6_14 29 I/O (unused) 0 FB6_15 (b) (unused) 0 FB6_16 30 I/O *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) (unused) 0 FB7_5 19 I/O (unused) 0 FB7_6 18 I/O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) (unused) 0 FB7_11 17 I/O (unused) 0 FB7_12 16 I/O (unused) 0 FB7_13 15 I/O (unused) 0 FB7_14 14 I/O (unused) 0 FB7_15 (b) (unused) 0 FB7_16 (b) *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 (b) (unused) 0 FB8_2 (b) (unused) 0 FB8_3 (b) (unused) 0 FB8_4 (b) (unused) 0 FB8_5 (b) (unused) 0 FB8_6 32 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 33 I/O (unused) 0 FB8_12 34 I/O (unused) 0 FB8_13 35 I/O (unused) 0 FB8_14 36 I/O (unused) 0 FB8_15 37 I/O (unused) 0 FB8_16 (b) *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 5/35 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 12/44 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use seg<0> 3 FB9_1 78 I/O O seg<5> 3 FB9_2 79 I/O O (unused) 0 FB9_3 (b) dig<0> 1 FB9_4 80 I/O O (unused) 0 FB9_5 (b) seg<3> 4 FB9_6 81 I/O O (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) seg<4> 3 FB9_12 82 I/O O (unused) 0 FB9_13 (b) (unused) 0 FB9_14 (b) (unused) 0 FB9_15 (b) (unused) 0 FB9_16 (b) Signals Used by Logic in Function Block 1: u_led_7_seg/cnt_1d<18> 3: u_led_7_seg/disp_data_r<1> 5: u_led_7_seg/disp_data_r<3> 2: u_led_7_seg/disp_data_r<0> 4: u_led_7_seg/disp_data_r<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs seg<0> .XXXX................................... 4 seg<5> .XXXX................................... 4 dig<0> X....................................... 1 seg<3> .XXXX................................... 4 seg<4> .XXXX................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 4/36 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 3/53 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use seg<7> 0 FB10_1 77 I/O O seg<6> 3 FB10_2 76 I/O O (unused) 0 FB10_3 74 I/O (unused) 0 FB10_4 73 I/O (unused) 0 FB10_5 72 I/O (unused) 0 FB10_6 71 I/O (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) (unused) 0 FB10_12 70 I/O (unused) 0 FB10_13 (b) (unused) 0 FB10_14 (b) (unused) 0 FB10_15 (b) (unused) 0 FB10_16 (b) Signals Used by Logic in Function Block 1: u_led_7_seg/disp_data_r<0> 3: u_led_7_seg/disp_data_r<2> 4: u_led_7_seg/disp_data_r<3> 2: u_led_7_seg/disp_data_r<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs seg<7> ........................................ 0 seg<6> XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 5/35 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 7/49 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) (unused) 0 FB11_5 (b) (unused) 0 FB11_6 (b) (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) seg<2> 3 FB11_11 85 I/O O seg<1> 3 FB11_12 86 I/O O dig<1> 1 FB11_13 87 I/O O (unused) 0 FB11_14 89 I/O (unused) 0 FB11_15 (b) (unused) 0 FB11_16 (b) Signals Used by Logic in Function Block 1: u_led_7_seg/cnt_1d<18> 3: u_led_7_seg/disp_data_r<1> 5: u_led_7_seg/disp_data_r<3> 2: u_led_7_seg/disp_data_r<0> 4: u_led_7_seg/disp_data_r<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs seg<2> .XXXX................................... 4 seg<1> .XXXX................................... 4 dig<1> X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 (b) (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 68 I/O (unused) 0 FB12_12 (b) (unused) 0 FB12_13 67 I/O (unused) 0 FB12_14 66 I/O (unused) 0 FB12_15 65 I/O (unused) 0 FB12_16 (b) *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 (b) (unused) 0 FB13_2 53 I/O (unused) 0 FB13_3 (b) (unused) 0 FB13_4 54 I/O (unused) 0 FB13_5 (b) (unused) 0 FB13_6 55 I/O (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 (b) (unused) 0 FB13_13 56 I/O (unused) 0 FB13_14 (b) (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 52 I/O (unused) 0 FB14_2 (b) (unused) 0 FB14_3 50 I/O (unused) 0 FB14_4 (b) (unused) 0 FB14_5 49 I/O (unused) 0 FB14_6 (b) (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) (unused) 0 FB14_13 (b) (unused) 0 FB14_14 46 I/O (unused) 0 FB14_15 44 I/O (unused) 0 FB14_16 (b) *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) (unused) 0 FB15_2 (b) (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 58 I/O (unused) 0 FB15_12 59 I/O (unused) 0 FB15_13 60 I/O (unused) 0 FB15_14 61 I/O (unused) 0 FB15_15 63 I/O (unused) 0 FB15_16 64 I/O *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) (unused) 0 FB16_5 43 I/O (unused) 0 FB16_6 42 I/O (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) (unused) 0 FB16_11 41 I/O (unused) 0 FB16_12 40 I/O (unused) 0 FB16_13 39 I/O (unused) 0 FB16_14 (b) (unused) 0 FB16_15 (b) (unused) 0 FB16_16 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_dig0: FDCPE port map (dig(0),u_led_7_seg/cnt_1d(18),clk,'0',NOT reset_n,'1'); FDCPE_dig1: FDCPE port map (dig(1),NOT u_led_7_seg/cnt_1d(18),clk,'0',NOT reset_n,'1'); FTCPE_ps2_scan_code0: FTCPE port map (ps2_scan_code(0),ps2_scan_code_T(0),clk,NOT reset_n,'0','1'); ps2_scan_code_T(0) <= ((u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0 AND ps2_scan_code(0)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND ps2_scan_code(0)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/key_f0 AND u_ps2scan/temp_data(0) AND NOT ps2_scan_code(0))); FTCPE_ps2_scan_code1: FTCPE port map (ps2_scan_code(1),ps2_scan_code_T(1),clk,NOT reset_n,'0','1'); ps2_scan_code_T(1) <= ((u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0 AND ps2_scan_code(1)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(1) AND ps2_scan_code(1)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/key_f0 AND u_ps2scan/temp_data(1) AND NOT ps2_scan_code(1))); FTCPE_ps2_scan_code2: FTCPE port map (ps2_scan_code(2),ps2_scan_code_T(2),clk,NOT reset_n,'0','1'); ps2_scan_code_T(2) <= ((u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0 AND ps2_scan_code(2)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(2) AND ps2_scan_code(2)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/key_f0 AND u_ps2scan/temp_data(2) AND NOT ps2_scan_code(2))); FTCPE_ps2_scan_code3: FTCPE port map (ps2_scan_code(3),ps2_scan_code_T(3),clk,NOT reset_n,'0','1'); ps2_scan_code_T(3) <= ((u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0 AND ps2_scan_code(3)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(3) AND ps2_scan_code(3)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/key_f0 AND u_ps2scan/temp_data(3) AND NOT ps2_scan_code(3))); FDCPE_ps2_scan_code4: FDCPE port map (ps2_scan_code(4),ps2_scan_code_D(4),clk,NOT reset_n,'0','1'); ps2_scan_code_D(4) <= NOT (((NOT u_ps2scan/num_FSM_FFd1 AND NOT ps2_scan_code(4)) OR (u_ps2scan/ps2_clk_1d AND NOT ps2_scan_code(4)) OR (NOT u_ps2scan/ps2_clk_2d AND NOT ps2_scan_code(4)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(4)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND NOT u_ps2scan/temp_data(1) AND NOT u_ps2scan/temp_data(2) AND NOT u_ps2scan/temp_data(3) AND u_ps2scan/temp_data(5) AND u_ps2scan/temp_data(6) AND u_ps2scan/temp_data(7)))); FDCPE_ps2_scan_code5: FDCPE port map (ps2_scan_code(5),ps2_scan_code_D(5),clk,NOT reset_n,'0','1'); ps2_scan_code_D(5) <= NOT (((NOT ps2_scan_code(5) AND NOT u_ps2scan/num_FSM_FFd1) OR (NOT ps2_scan_code(5) AND u_ps2scan/ps2_clk_1d) OR (NOT ps2_scan_code(5) AND NOT u_ps2scan/ps2_clk_2d) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(5)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND NOT u_ps2scan/temp_data(1) AND NOT u_ps2scan/temp_data(2) AND NOT u_ps2scan/temp_data(3) AND u_ps2scan/temp_data(4) AND u_ps2scan/temp_data(6) AND u_ps2scan/temp_data(7)))); FDCPE_ps2_scan_code6: FDCPE port map (ps2_scan_code(6),ps2_scan_code_D(6),clk,NOT reset_n,'0','1'); ps2_scan_code_D(6) <= NOT (((NOT u_ps2scan/num_FSM_FFd1 AND NOT ps2_scan_code(6)) OR (u_ps2scan/ps2_clk_1d AND NOT ps2_scan_code(6)) OR (NOT u_ps2scan/ps2_clk_2d AND NOT ps2_scan_code(6)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(6)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND NOT u_ps2scan/temp_data(1) AND NOT u_ps2scan/temp_data(2) AND NOT u_ps2scan/temp_data(3) AND u_ps2scan/temp_data(4) AND u_ps2scan/temp_data(5) AND u_ps2scan/temp_data(7)))); FDCPE_ps2_scan_code7: FDCPE port map (ps2_scan_code(7),ps2_scan_code_D(7),clk,NOT reset_n,'0','1'); ps2_scan_code_D(7) <= NOT (((NOT u_ps2scan/num_FSM_FFd1 AND NOT ps2_scan_code(7)) OR (u_ps2scan/ps2_clk_1d AND NOT ps2_scan_code(7)) OR (NOT u_ps2scan/ps2_clk_2d AND NOT ps2_scan_code(7)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(7)) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND NOT u_ps2scan/temp_data(1) AND NOT u_ps2scan/temp_data(2) AND NOT u_ps2scan/temp_data(3) AND u_ps2scan/temp_data(4) AND u_ps2scan/temp_data(5) AND u_ps2scan/temp_data(6)))); FDCPE_seg0: FDCPE port map (seg(0),seg_D(0),clk,NOT reset_n,'0','1'); seg_D(0) <= (NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0)) XOR ((NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3)) OR (u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2) AND u_led_7_seg/disp_data_r(3))); FDCPE_seg1: FDCPE port map (seg(1),seg_D(1),clk,NOT reset_n,'0','1'); seg_D(1) <= (NOT u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2)) XOR ((u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3))); FDCPE_seg2: FDCPE port map (seg(2),seg_D(2),clk,NOT reset_n,'0','1'); seg_D(2) <= ((u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(2) AND u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2) AND u_led_7_seg/disp_data_r(3)) OR (u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3))); FDCPE_seg3: FDCPE port map (seg(3),seg_D(3),clk,NOT reset_n,'0','1'); seg_D(3) <= ((u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2)) OR (u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2) AND u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3))); FDCPE_seg4: FDCPE port map (seg(4),seg_D(4),clk,NOT reset_n,'0','1'); seg_D(4) <= ((u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2)) OR (NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3))); FDCPE_seg5: FDCPE port map (seg(5),seg_D(5),clk,NOT reset_n,'0','1'); seg_D(5) <= (u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(3)) XOR ((NOT u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2)) OR (u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(0) AND NOT u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3))); FDCPE_seg6: FDCPE port map (seg(6),seg_D(6),clk,NOT reset_n,'0','1'); seg_D(6) <= ((NOT u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3)) OR (u_led_7_seg/disp_data_r(1) AND u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2) AND NOT u_led_7_seg/disp_data_r(3)) OR (NOT u_led_7_seg/disp_data_r(1) AND NOT u_led_7_seg/disp_data_r(0) AND u_led_7_seg/disp_data_r(2) AND u_led_7_seg/disp_data_r(3))); FDCPE_seg7: FDCPE port map (seg(7),NOT '0',clk,NOT reset_n,'0','1'); FTCPE_u_led_7_seg/cnt0: FTCPE port map (u_led_7_seg/cnt(0),'0',clk,NOT reset_n,'0','1'); FTCPE_u_led_7_seg/cnt1: FTCPE port map (u_led_7_seg/cnt(1),u_led_7_seg/cnt(0),clk,NOT reset_n,'0','1'); FTCPE_u_led_7_seg/cnt2: FTCPE port map (u_led_7_seg/cnt(2),u_led_7_seg/cnt_T(2),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(2) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1)); FTCPE_u_led_7_seg/cnt3: FTCPE port map (u_led_7_seg/cnt(3),u_led_7_seg/cnt_T(3),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(3) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2)); FTCPE_u_led_7_seg/cnt4: FTCPE port map (u_led_7_seg/cnt(4),u_led_7_seg/cnt_T(4),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(4) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3)); FTCPE_u_led_7_seg/cnt5: FTCPE port map (u_led_7_seg/cnt(5),u_led_7_seg/cnt_T(5),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(5) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4)); FTCPE_u_led_7_seg/cnt6: FTCPE port map (u_led_7_seg/cnt(6),u_led_7_seg/cnt_T(6),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(6) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5)); FTCPE_u_led_7_seg/cnt7: FTCPE port map (u_led_7_seg/cnt(7),u_led_7_seg/cnt_T(7),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(7) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6)); FTCPE_u_led_7_seg/cnt8: FTCPE port map (u_led_7_seg/cnt(8),u_led_7_seg/cnt_T(8),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(8) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7)); FTCPE_u_led_7_seg/cnt9: FTCPE port map (u_led_7_seg/cnt(9),u_led_7_seg/cnt_T(9),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(9) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8)); FTCPE_u_led_7_seg/cnt10: FTCPE port map (u_led_7_seg/cnt(10),u_led_7_seg/cnt_T(10),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(10) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9)); FTCPE_u_led_7_seg/cnt11: FTCPE port map (u_led_7_seg/cnt(11),u_led_7_seg/cnt_T(11),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(11) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9)); FTCPE_u_led_7_seg/cnt12: FTCPE port map (u_led_7_seg/cnt(12),u_led_7_seg/cnt_T(12),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(12) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11)); FTCPE_u_led_7_seg/cnt13: FTCPE port map (u_led_7_seg/cnt(13),u_led_7_seg/cnt_T(13),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(13) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12)); FTCPE_u_led_7_seg/cnt14: FTCPE port map (u_led_7_seg/cnt(14),u_led_7_seg/cnt_T(14),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(14) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12) AND u_led_7_seg/cnt(13)); FTCPE_u_led_7_seg/cnt15: FTCPE port map (u_led_7_seg/cnt(15),u_led_7_seg/cnt_T(15),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(15) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12) AND u_led_7_seg/cnt(13) AND u_led_7_seg/cnt(14)); FTCPE_u_led_7_seg/cnt16: FTCPE port map (u_led_7_seg/cnt(16),u_led_7_seg/cnt_T(16),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(16) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12) AND u_led_7_seg/cnt(13) AND u_led_7_seg/cnt(14) AND u_led_7_seg/cnt(15)); FTCPE_u_led_7_seg/cnt17: FTCPE port map (u_led_7_seg/cnt(17),u_led_7_seg/cnt_T(17),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(17) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12) AND u_led_7_seg/cnt(13) AND u_led_7_seg/cnt(14) AND u_led_7_seg/cnt(15) AND u_led_7_seg/cnt(16)); FTCPE_u_led_7_seg/cnt18: FTCPE port map (u_led_7_seg/cnt(18),u_led_7_seg/cnt_T(18),clk,NOT reset_n,'0','1'); u_led_7_seg/cnt_T(18) <= (u_led_7_seg/cnt(0) AND u_led_7_seg/cnt(10) AND u_led_7_seg/cnt(1) AND u_led_7_seg/cnt(2) AND u_led_7_seg/cnt(3) AND u_led_7_seg/cnt(4) AND u_led_7_seg/cnt(5) AND u_led_7_seg/cnt(6) AND u_led_7_seg/cnt(7) AND u_led_7_seg/cnt(8) AND u_led_7_seg/cnt(9) AND u_led_7_seg/cnt(11) AND u_led_7_seg/cnt(12) AND u_led_7_seg/cnt(13) AND u_led_7_seg/cnt(14) AND u_led_7_seg/cnt(15) AND u_led_7_seg/cnt(16) AND u_led_7_seg/cnt(17)); FDCPE_u_led_7_seg/cnt_1d18: FDCPE port map (u_led_7_seg/cnt_1d(18),u_led_7_seg/cnt(18),clk,NOT reset_n,'0','1'); FDCPE_u_led_7_seg/disp_data_r0: FDCPE port map (u_led_7_seg/disp_data_r(0),u_led_7_seg/disp_data_r_D(0),clk,NOT reset_n,'0','1'); u_led_7_seg/disp_data_r_D(0) <= NOT (((u_led_7_seg/cnt(18) AND NOT ps2_scan_code(4)) OR (NOT u_led_7_seg/cnt(18) AND NOT ps2_scan_code(0)))); FDCPE_u_led_7_seg/disp_data_r1: FDCPE port map (u_led_7_seg/disp_data_r(1),u_led_7_seg/disp_data_r_D(1),clk,NOT reset_n,'0','1'); u_led_7_seg/disp_data_r_D(1) <= NOT (((u_led_7_seg/cnt(18) AND NOT ps2_scan_code(5)) OR (NOT u_led_7_seg/cnt(18) AND NOT ps2_scan_code(1)))); FDCPE_u_led_7_seg/disp_data_r2: FDCPE port map (u_led_7_seg/disp_data_r(2),u_led_7_seg/disp_data_r_D(2),clk,NOT reset_n,'0','1'); u_led_7_seg/disp_data_r_D(2) <= NOT (((u_led_7_seg/cnt(18) AND NOT ps2_scan_code(6)) OR (NOT u_led_7_seg/cnt(18) AND NOT ps2_scan_code(2)))); FDCPE_u_led_7_seg/disp_data_r3: FDCPE port map (u_led_7_seg/disp_data_r(3),u_led_7_seg/disp_data_r_D(3),clk,NOT reset_n,'0','1'); u_led_7_seg/disp_data_r_D(3) <= NOT (((u_led_7_seg/cnt(18) AND NOT ps2_scan_code(7)) OR (NOT u_led_7_seg/cnt(18) AND NOT ps2_scan_code(3)))); FDCPE_u_ps2scan/key_f0: FDCPE port map (u_ps2scan/key_f0,u_ps2scan/key_f0_D,clk,NOT reset_n,'0','1'); u_ps2scan/key_f0_D <= ((NOT u_ps2scan/num_FSM_FFd1 AND u_ps2scan/key_f0) OR (u_ps2scan/ps2_clk_1d AND u_ps2scan/key_f0) OR (NOT u_ps2scan/ps2_clk_2d AND u_ps2scan/key_f0) OR (u_ps2scan/num_FSM_FFd1 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND NOT u_ps2scan/temp_data(1) AND NOT u_ps2scan/temp_data(2) AND NOT u_ps2scan/temp_data(3) AND u_ps2scan/temp_data(4) AND u_ps2scan/temp_data(5) AND u_ps2scan/temp_data(6) AND u_ps2scan/temp_data(7))); FDCPE_u_ps2scan/num_FSM_FFd10: FDCPE port map (u_ps2scan/num_FSM_FFd10,u_ps2scan/num_FSM_FFd11,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd10_CE); u_ps2scan/num_FSM_FFd10_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd11: FDCPE port map (u_ps2scan/num_FSM_FFd11,u_ps2scan/num_FSM_FFd1,clk,'0',NOT reset_n,u_ps2scan/num_FSM_FFd11_CE); u_ps2scan/num_FSM_FFd11_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd1: FDCPE port map (u_ps2scan/num_FSM_FFd1,u_ps2scan/num_FSM_FFd2,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd1_CE); u_ps2scan/num_FSM_FFd1_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd2: FDCPE port map (u_ps2scan/num_FSM_FFd2,u_ps2scan/num_FSM_FFd3,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd2_CE); u_ps2scan/num_FSM_FFd2_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd3: FDCPE port map (u_ps2scan/num_FSM_FFd3,u_ps2scan/num_FSM_FFd4,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd3_CE); u_ps2scan/num_FSM_FFd3_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd4: FDCPE port map (u_ps2scan/num_FSM_FFd4,u_ps2scan/num_FSM_FFd5,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd4_CE); u_ps2scan/num_FSM_FFd4_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd5: FDCPE port map (u_ps2scan/num_FSM_FFd5,u_ps2scan/num_FSM_FFd6,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd5_CE); u_ps2scan/num_FSM_FFd5_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd6: FDCPE port map (u_ps2scan/num_FSM_FFd6,u_ps2scan/num_FSM_FFd7,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd6_CE); u_ps2scan/num_FSM_FFd6_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd7: FDCPE port map (u_ps2scan/num_FSM_FFd7,u_ps2scan/num_FSM_FFd8,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd7_CE); u_ps2scan/num_FSM_FFd7_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd8: FDCPE port map (u_ps2scan/num_FSM_FFd8,u_ps2scan/num_FSM_FFd9,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd8_CE); u_ps2scan/num_FSM_FFd8_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/num_FSM_FFd9: FDCPE port map (u_ps2scan/num_FSM_FFd9,u_ps2scan/num_FSM_FFd10,clk,NOT reset_n,'0',u_ps2scan/num_FSM_FFd9_CE); u_ps2scan/num_FSM_FFd9_CE <= (NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d); FDCPE_u_ps2scan/ps2_clk_1d: FDCPE port map (u_ps2scan/ps2_clk_1d,ps2_clk,clk,NOT reset_n,'0','1'); FDCPE_u_ps2scan/ps2_clk_2d: FDCPE port map (u_ps2scan/ps2_clk_2d,u_ps2scan/ps2_clk_1d,clk,NOT reset_n,'0','1'); FTCPE_u_ps2scan/temp_data0: FTCPE port map (u_ps2scan/temp_data(0),u_ps2scan/temp_data_T(0),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(0) <= ((u_ps2scan/num_FSM_FFd10 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(0) AND NOT ps2_data) OR (u_ps2scan/num_FSM_FFd10 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT u_ps2scan/temp_data(0) AND ps2_data) OR (NOT u_ps2scan/num_FSM_FFd10 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(0))); FTCPE_u_ps2scan/temp_data1: FTCPE port map (u_ps2scan/temp_data(1),u_ps2scan/temp_data_T(1),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(1) <= ((u_ps2scan/num_FSM_FFd9 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(1)) OR (u_ps2scan/num_FSM_FFd9 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(1)) OR (NOT u_ps2scan/num_FSM_FFd9 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(1))); FTCPE_u_ps2scan/temp_data2: FTCPE port map (u_ps2scan/temp_data(2),u_ps2scan/temp_data_T(2),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(2) <= ((u_ps2scan/num_FSM_FFd8 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(2)) OR (u_ps2scan/num_FSM_FFd8 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(2)) OR (NOT u_ps2scan/num_FSM_FFd8 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(2))); FTCPE_u_ps2scan/temp_data3: FTCPE port map (u_ps2scan/temp_data(3),u_ps2scan/temp_data_T(3),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(3) <= ((u_ps2scan/num_FSM_FFd7 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(3)) OR (u_ps2scan/num_FSM_FFd7 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(3)) OR (NOT u_ps2scan/num_FSM_FFd7 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(3))); FTCPE_u_ps2scan/temp_data4: FTCPE port map (u_ps2scan/temp_data(4),u_ps2scan/temp_data_T(4),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(4) <= ((u_ps2scan/num_FSM_FFd6 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(4)) OR (u_ps2scan/num_FSM_FFd6 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(4)) OR (NOT u_ps2scan/num_FSM_FFd6 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(4))); FTCPE_u_ps2scan/temp_data5: FTCPE port map (u_ps2scan/temp_data(5),u_ps2scan/temp_data_T(5),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(5) <= ((u_ps2scan/num_FSM_FFd5 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(5)) OR (u_ps2scan/num_FSM_FFd5 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(5)) OR (NOT u_ps2scan/num_FSM_FFd5 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(5))); FTCPE_u_ps2scan/temp_data6: FTCPE port map (u_ps2scan/temp_data(6),u_ps2scan/temp_data_T(6),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(6) <= ((u_ps2scan/num_FSM_FFd4 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(6)) OR (u_ps2scan/num_FSM_FFd4 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(6)) OR (NOT u_ps2scan/num_FSM_FFd4 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(6))); FTCPE_u_ps2scan/temp_data7: FTCPE port map (u_ps2scan/temp_data(7),u_ps2scan/temp_data_T(7),clk,NOT reset_n,'0','1'); u_ps2scan/temp_data_T(7) <= ((u_ps2scan/num_FSM_FFd3 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND ps2_data AND NOT u_ps2scan/temp_data(7)) OR (u_ps2scan/num_FSM_FFd3 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND NOT ps2_data AND u_ps2scan/temp_data(7)) OR (NOT u_ps2scan/num_FSM_FFd3 AND u_ps2scan/num_FSM_FFd11 AND NOT u_ps2scan/ps2_clk_1d AND u_ps2scan/ps2_clk_2d AND u_ps2scan/temp_data(7))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-7-VQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC2C256-7-VQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 51 VCCIO-1.8 2 TIE 52 TIE 3 TIE 53 TIE 4 TIE 54 TIE 5 VCCAUX 55 TIE 6 TIE 56 TIE 7 TIE 57 VCC 8 TIE 58 TIE 9 TIE 59 TIE 10 ps2_clk 60 TIE 11 ps2_data 61 TIE 12 TIE 62 GND 13 TIE 63 TIE 14 TIE 64 TIE 15 TIE 65 TIE 16 TIE 66 TIE 17 TIE 67 TIE 18 TIE 68 TIE 19 TIE 69 GND 20 VCCIO-1.8 70 TIE 21 GND 71 TIE 22 clk 72 TIE 23 TIE 73 TIE 24 TIE 74 TIE 25 GND 75 GND 26 VCC 76 seg<6> 27 TIE 77 seg<7> 28 TIE 78 seg<0> 29 TIE 79 seg<5> 30 TIE 80 dig<0> 31 GND 81 seg<3> 32 TIE 82 seg<4> 33 TIE 83 TDO 34 TIE 84 GND 35 TIE 85 seg<2> 36 TIE 86 seg<1> 37 TIE 87 dig<1> 38 VCCIO-1.8 88 VCCIO-1.8 39 TIE 89 TIE 40 TIE 90 TIE 41 TIE 91 TIE 42 TIE 92 TIE 43 TIE 93 TIE 44 TIE 94 TIE 45 TDI 95 TIE 46 TIE 96 TIE 47 TMS 97 TIE 48 TCK 98 VCCIO-1.8 49 TIE 99 reset_n 50 TIE 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-7-VQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28