cpldfit:  version M.70d                             Xilinx Inc.
                                  Fitter Report
Design Name: vga                                 Date:  9-25-2013,  0:07AM
Device Used: XC2C256-7-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
42 /256 ( 16%) 138 /896  ( 15%) 101 /640  ( 16%) 41 /256 ( 16%) 7  /80  (  9%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    14/40    17/56     0/ 5    0/1      0/1      0/1      0/1
FB2      16/16*    27/40    53/56     0/ 6    0/1      0/1      0/1      0/1
FB3       5/16     10/40    24/56     0/ 4    0/1      0/1      0/1      0/1
FB4       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB5       0/16      0/40     0/56     0/ 2    0/1      0/1      0/1      0/1
FB6       4/16     38/40*   24/56     4/ 5    0/1      0/1      0/1      0/1
FB7       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB8       1/16     12/40    20/56     1/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    42/256   101/640  138/896    5/80    0/16     0/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         DGE         
Used/Tot    Used/Tot    Used/Tot    Used/Tot    
1/3         1/1         0/4         0/1

Signal 'clk' mapped onto global clock net GCK0.
Signal 'reset_n' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :     3     70
Output        :    5           5    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     0      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  CDR/IO           :     0      1
GSR           :    1           1    |  DGE/IO           :     1      1
                 ----        ----
        Total      7           7

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'vga.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC
   constraint 'P22'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
*************************  Summary of Mapped Logic  ************************

** 5 Outputs **

Signal              Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
vga_hsync           2     13    1    FB6_4   27    GCK/I/O   O       LVCMOS18           FAST TFF     RESET
vga_vsync           2     13    1    FB6_12  28    DGE/I/O   O       LVCMOS18           FAST TFF     RESET
vga_r               8     10    1    FB6_14  29    I/O       O       LVCMOS18           FAST DFF     RESET
vga_g               12    11    1    FB6_16  30    I/O       O       LVCMOS18           FAST DFF     RESET
vga_b               20    12    1    FB8_6   32    I/O       O       LVCMOS18           FAST DFF     RESET

** 37 Buried Nodes **

Signal              Total Total Loc     Reg     Reg Init
Name                Pts   Inps          Use     State
x_cnt<9>            1     9     FB1_1   TFF     RESET
x_cnt<8>            1     8     FB1_2   TFF     RESET
y_cnt<2>            1     14    FB1_3   TFF     RESET
x_cnt<7>            1     7     FB1_4   TFF     RESET
x_cnt<6>            1     6     FB1_5   TFF     RESET
x_cnt<4>            5     12    FB1_6   TFF     RESET
x_cnt<5>            1     5     FB1_7   TFF     RESET
x_cnt<3>            1     3     FB1_8   TFF     RESET
x_cnt<2>            1     2     FB1_9   TFF     RESET
x_cnt<1>            1     1     FB1_10  TFF     RESET
x_dis<11>           0     0     FB1_11  DFF     RESET
x_cnt<10>           2     12    FB1_12  TFF     RESET
y_cnt<0>            1     12    FB1_13  TFF     RESET
x_cnt<11>           1     11    FB1_14  TFF     RESET
x_dis<10>           0     0     FB1_15  DFF     RESET
x_cnt<0>            0     0     FB1_16  TFF     RESET
x_dis<5>            8     10    FB2_1   DFF     RESET
y_cnt<5>            1     17    FB2_2   TFF     RESET
x_dis<4>            7     10    FB2_3   DFF     RESET
y_cnt<6>            1     18    FB2_4   TFF     RESET
x_dis<2>            7     10    FB2_5   DFF     RESET
y_cnt<8>            1     20    FB2_6   TFF     RESET
y_cnt<10>           1     22    FB2_7   TFF     RESET
y_cnt<11>           1     23    FB2_8   TFF     RESET
y_cnt<4>            3     24    FB2_9   DFF     RESET
y_cnt<3>            3     24    FB2_10  DFF     RESET
y_cnt<7>            3     24    FB2_11  DFF     RESET
x_dis<6>            6     10    FB2_12  DFF     RESET
y_cnt<9>            3     24    FB2_13  DFF     RESET
valid               2     15    FB2_14  TFF     RESET
valid_y             2     13    FB2_15  TFF     RESET
y_cnt<1>            11    24    FB2_16  TFF     RESET
N_PZ_299            1     2     FB3_9           
x_dis<7>            5     8     FB3_10  DFF     RESET
x_dis<3>            4     8     FB3_11  DFF     RESET
x_dis<9>            6     9     FB3_13  DFF     RESET
x_dis<8>            8     9     FB3_15  DFF     RESET

** 2 Inputs **

Signal              Bank Loc     Pin   Pin       Pin     I/O      I/O
Name                             No.   Type      Use     STD      Style
reset_n             2    FB1_3   99    GSR/I/O   GSR     LVCMOS18 KPR
clk                 1    FB5_6   22    GCK/I/O   GCK     LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               14/26
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   17/39
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
x_cnt<9>                      1     FB1_1        (b)     (b)               
x_cnt<8>                      1     FB1_2        (b)     (b)               
y_cnt<2>                      1     FB1_3   99   GSR/I/O GSR               
x_cnt<7>                      1     FB1_4        (b)     (b)               
x_cnt<6>                      1     FB1_5        (b)     (b)               
x_cnt<4>                      5     FB1_6   97   I/O     (b)               
x_cnt<5>                      1     FB1_7        (b)     (b)               
x_cnt<3>                      1     FB1_8        (b)     (b)               
x_cnt<2>                      1     FB1_9        (b)     (b)               
x_cnt<1>                      1     FB1_10       (b)     (b)               
x_dis<11>                     0     FB1_11       (b)     (b)               
x_cnt<10>                     2     FB1_12  96   I/O     (b)               
y_cnt<0>                      1     FB1_13  95   I/O     (b)               
x_cnt<11>                     1     FB1_14  94   I/O     (b)               
x_dis<10>                     0     FB1_15       (b)     (b)               
x_cnt<0>                      0     FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: x_cnt<0>           6: x_cnt<3>          11: x_cnt<8> 
  2: x_cnt<10>          7: x_cnt<4>          12: x_cnt<9> 
  3: x_cnt<11>          8: x_cnt<5>          13: y_cnt<0> 
  4: x_cnt<1>           9: x_cnt<6>          14: y_cnt<1> 
  5: x_cnt<2>          10: x_cnt<7>         

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
x_cnt<9>          X..XXXXXXXX............................. 9       
x_cnt<8>          X..XXXXXXX.............................. 8       
y_cnt<2>          XXXXXXXXXXXXXX.......................... 14      
x_cnt<7>          X..XXXXXX............................... 7       
x_cnt<6>          X..XXXXX................................ 6       
x_cnt<4>          XXXXXXXXXXXX............................ 12      
x_cnt<5>          X..XXXX................................. 5       
x_cnt<3>          X..XX................................... 3       
x_cnt<2>          X..X.................................... 2       
x_cnt<1>          X....................................... 1       
x_dis<11>         ........................................ 0       
x_cnt<10>         XXXXXXXXXXXX............................ 12      
y_cnt<0>          XXXXXXXXXXXX............................ 12      
x_cnt<11>         XX.XXXXXXXXX............................ 11      
x_dis<10>         ........................................ 0       
x_cnt<0>          ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               27/13
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   53/3
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
x_dis<5>                      8     FB2_1   1    GTS/I/O (b)               
y_cnt<5>                      1     FB2_2        (b)     (b)               
x_dis<4>                      7     FB2_3   2    GTS/I/O (b)               
y_cnt<6>                      1     FB2_4        (b)     (b)               
x_dis<2>                      7     FB2_5   3    GTS/I/O (b)               
y_cnt<8>                      1     FB2_6        (b)     (b)               
y_cnt<10>                     1     FB2_7        (b)     (b)               
y_cnt<11>                     1     FB2_8        (b)     (b)               
y_cnt<4>                      3     FB2_9        (b)     (b)               
y_cnt<3>                      3     FB2_10       (b)     (b)               
y_cnt<7>                      3     FB2_11       (b)     (b)               
x_dis<6>                      6     FB2_12  4    GTS/I/O (b)               
y_cnt<9>                      3     FB2_13       (b)     (b)               
valid                         2     FB2_14  6    I/O     (b)               
valid_y                       2     FB2_15  7    I/O     (b)               
y_cnt<1>                      11    FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: N_PZ_299          10: x_cnt<4>          19: y_cnt<1> 
  2: valid             11: x_cnt<5>          20: y_cnt<2> 
  3: valid_y           12: x_cnt<6>          21: y_cnt<3> 
  4: x_cnt<0>          13: x_cnt<7>          22: y_cnt<4> 
  5: x_cnt<10>         14: x_cnt<8>          23: y_cnt<5> 
  6: x_cnt<11>         15: x_cnt<9>          24: y_cnt<6> 
  7: x_cnt<1>          16: y_cnt<0>          25: y_cnt<7> 
  8: x_cnt<2>          17: y_cnt<10>         26: y_cnt<8> 
  9: x_cnt<3>          18: y_cnt<11>         27: y_cnt<9> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
x_dis<5>          X...XX..XXXXXXX......................... 10      
y_cnt<5>          ...XXXXXXXXXXXXX..XXXX.................. 17      
x_dis<4>          X...XX..XXXXXXX......................... 10      
y_cnt<6>          ...XXXXXXXXXXXXX..XXXXX................. 18      
x_dis<2>          ....XX.XXXXXXXX......................... 10      
y_cnt<8>          ...XXXXXXXXXXXXX..XXXXXXX............... 20      
y_cnt<10>         ...XXXXXXXXXXXXX..XXXXXXXXX............. 22      
y_cnt<11>         ...XXXXXXXXXXXXXX.XXXXXXXXX............. 23      
y_cnt<4>          ...XXXXXXXXXXXXXXXXXXXXXXXX............. 24      
y_cnt<3>          ...XXXXXXXXXXXXXXXXXXXXXXXX............. 24      
y_cnt<7>          ...XXXXXXXXXXXXXXXXXXXXXXXX............. 24      
x_dis<6>          X...XX..XXXXXXX......................... 10      
y_cnt<9>          ...XXXXXXXXXXXXXXXXXXXXXXXX............. 24      
valid             XXXXXXXXXXXXXXX......................... 15      
valid_y           ..X............XXXXXXXXXXXX............. 13      
y_cnt<1>          ...XXXXXXXXXXXXXXXXXXXXXXXX............. 24      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               10/30
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   24/32
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB3_1        (b)           
(unused)                      0     FB3_2        (b)           
(unused)                      0     FB3_3        (b)           
(unused)                      0     FB3_4        (b)           
(unused)                      0     FB3_5   93   I/O           
(unused)                      0     FB3_6        (b)           
(unused)                      0     FB3_7        (b)           
(unused)                      0     FB3_8        (b)           
N_PZ_299                      1     FB3_9        (b)     (b)               
x_dis<7>                      5     FB3_10       (b)     (b)               
x_dis<3>                      4     FB3_11       (b)     (b)               
(unused)                      0     FB3_12  92   I/O           
x_dis<9>                      6     FB3_13       (b)     (b)               
(unused)                      0     FB3_14  91   I/O           
x_dis<8>                      8     FB3_15       (b)     (b)               
(unused)                      0     FB3_16  90   I/O           

Signals Used by Logic in Function Block
  1: N_PZ_299           5: x_cnt<4>           8: x_cnt<7> 
  2: x_cnt<10>          6: x_cnt<5>           9: x_cnt<8> 
  3: x_cnt<11>          7: x_cnt<6>          10: x_cnt<9> 
  4: x_cnt<3>         

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_PZ_299          ........XX.............................. 2       
x_dis<7>          XXXXXXXX................................ 8       
x_dis<3>          .XXX.XXXXX.............................. 8       
x_dis<9>          .XXXXXXXXX.............................. 9       
x_dis<8>          .XXXXXXXXX.............................. 9       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB4_1   8    I/O           
(unused)                      0     FB4_2   9    I/O           
(unused)                      0     FB4_3   10   I/O           
(unused)                      0     FB4_4        (b)           
(unused)                      0     FB4_5   11   I/O           
(unused)                      0     FB4_6   12   I/O           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
(unused)                      0     FB4_10       (b)           
(unused)                      0     FB4_11       (b)           
(unused)                      0     FB4_12       (b)           
(unused)                      0     FB4_13  13   I/O           
(unused)                      0     FB4_14       (b)           
(unused)                      0     FB4_15       (b)           
(unused)                      0     FB4_16       (b)           
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
(unused)                      0     FB5_2        (b)           
(unused)                      0     FB5_3        (b)           
(unused)                      0     FB5_4   23   GCK/I/O       
(unused)                      0     FB5_5        (b)           
(unused)                      0     FB5_6   22   GCK/I/O GCK   
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
(unused)                      0     FB5_14       (b)           
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               38/2
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   24/32
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1        (b)           
(unused)                      0     FB6_2   24   CDR/I/O       
(unused)                      0     FB6_3        (b)           
vga_hsync                     2     FB6_4   27   GCK/I/O O                 
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
vga_vsync                     2     FB6_12  28   DGE/I/O O                 
(unused)                      0     FB6_13       (b)           
vga_r                         8     FB6_14  29   I/O     O                 
(unused)                      0     FB6_15       (b)           
vga_g                         12    FB6_16  30   I/O     O                 

Signals Used by Logic in Function Block
  1: valid             14: x_cnt<6>          27: y_cnt<0> 
  2: vga_g             15: x_cnt<7>          28: y_cnt<10> 
  3: vga_hsync         16: x_cnt<8>          29: y_cnt<11> 
  4: vga_r             17: x_cnt<9>          30: y_cnt<1> 
  5: vga_vsync         18: x_dis<10>         31: y_cnt<2> 
  6: x_cnt<0>          19: x_dis<11>         32: y_cnt<3> 
  7: x_cnt<10>         20: x_dis<3>          33: y_cnt<4> 
  8: x_cnt<11>         21: x_dis<4>          34: y_cnt<5> 
  9: x_cnt<1>          22: x_dis<5>          35: y_cnt<6> 
 10: x_cnt<2>          23: x_dis<6>          36: y_cnt<7> 
 11: x_cnt<3>          24: x_dis<7>          37: y_cnt<8> 
 12: x_cnt<4>          25: x_dis<8>          38: y_cnt<9> 
 13: x_cnt<5>          26: x_dis<9>         

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
vga_hsync         ..X..XXXXXXXXXXXX....................... 13      
vga_vsync         ....X.....................XXXXXXXXXXXX.. 13      
vga_r             X..X.............XX.XXXXXX.............. 10      
vga_g             XX...............XXXXXXXXX.............. 11      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
(unused)                      0     FB7_5   19   I/O           
(unused)                      0     FB7_6   18   I/O           
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  17   I/O           
(unused)                      0     FB7_12  16   I/O           
(unused)                      0     FB7_13  15   I/O           
(unused)                      0     FB7_14  14   I/O           
(unused)                      0     FB7_15       (b)           
(unused)                      0     FB7_16       (b)           
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               12/28
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   20/36
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
vga_b                         20    FB8_6   32   I/O     O                 
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           

Signals Used by Logic in Function Block
  1: valid              5: x_dis<2>           9: x_dis<6> 
  2: vga_b              6: x_dis<3>          10: x_dis<7> 
  3: x_dis<10>          7: x_dis<4>          11: x_dis<8> 
  4: x_dis<11>          8: x_dis<5>          12: x_dis<9> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
vga_b             XXXXXXXXXXXX............................ 12      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O           
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
(unused)                      0     FB13_6  55   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
(unused)                      0     FB13_13 56   I/O           
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O           
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 58   I/O           
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********


N_PZ_299 <= (NOT x_cnt(8) AND NOT x_cnt(9));

FTCPE_valid: FTCPE port map (valid,valid_T,clk,NOT reset_n,'0','1');
valid_T <= ((x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND 
	NOT x_cnt(11) AND N_PZ_299 AND NOT valid AND valid_y)
	OR (x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND 
	NOT x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND 
	x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND valid AND valid_y));

FTCPE_valid_y: FTCPE port map (valid_y,valid_y_T,clk,NOT reset_n,'0','1');
valid_y_T <= ((valid_y AND y_cnt(0) AND NOT y_cnt(1) AND y_cnt(2) AND 
	NOT y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND y_cnt(9) AND 
	NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))
	OR (NOT valid_y AND y_cnt(0) AND NOT y_cnt(1) AND y_cnt(2) AND 
	y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND 
	NOT y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11)));

FDCPE_vga_b: FDCPE port map (vga_b,vga_b_D,clk,NOT reset_n,'0','1');
vga_b_D <= ((x_dis(10) AND valid AND vga_b)
	OR (x_dis(11) AND valid AND vga_b)
	OR (x_dis(9) AND valid AND x_dis(8) AND vga_b)
	OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid)
	OR (x_dis(6) AND x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8))
	OR (x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(8))
	OR (NOT x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8))
	OR (NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8))
	OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(4))
	OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(3))
	OR (x_dis(5) AND x_dis(6) AND NOT x_dis(7) AND NOT x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid AND x_dis(2))
	OR (x_dis(5) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8))
	OR (NOT x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(4) AND NOT x_dis(8))
	OR (NOT x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8) AND NOT x_dis(3))
	OR (NOT x_dis(5) AND NOT x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid AND NOT x_dis(4))
	OR (x_dis(5) AND x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8) AND x_dis(3))
	OR (x_dis(5) AND x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(4) AND x_dis(8) AND x_dis(2))
	OR (x_dis(5) AND NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(8) AND x_dis(3) AND x_dis(2))
	OR (NOT x_dis(5) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(4) AND NOT x_dis(8) AND NOT x_dis(3))
	OR (x_dis(5) AND NOT x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(4) AND NOT x_dis(8) AND x_dis(3) AND 
	x_dis(2)));

FDCPE_vga_g: FDCPE port map (vga_g,vga_g_D,clk,NOT reset_n,'0','1');
vga_g_D <= ((x_dis(10) AND valid AND vga_g)
	OR (x_dis(11) AND valid AND vga_g)
	OR (x_dis(9) AND valid AND x_dis(8) AND vga_g)
	OR (x_dis(7) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND NOT x_dis(8))
	OR (NOT x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND x_dis(8))
	OR (x_dis(5) AND x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8))
	OR (x_dis(5) AND x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(8))
	OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(8))
	OR (x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND x_dis(4) AND NOT x_dis(8))
	OR (x_dis(6) AND x_dis(7) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND NOT x_dis(8) AND x_dis(3))
	OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND NOT x_dis(4) AND x_dis(8))
	OR (x_dis(6) AND x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND x_dis(4) AND NOT x_dis(8) AND x_dis(3)));

FTCPE_vga_hsync: FTCPE port map (vga_hsync,vga_hsync_T,clk,'0',NOT reset_n,'1');
vga_hsync_T <= ((x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND NOT vga_hsync)
	OR (NOT x_cnt(3) AND NOT x_cnt(0) AND NOT x_cnt(2) AND NOT x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11) AND vga_hsync));

FDCPE_vga_r: FDCPE port map (vga_r,vga_r_D,clk,NOT reset_n,'0','1');
vga_r_D <= ((x_dis(9) AND valid AND vga_r)
	OR (x_dis(10) AND valid AND vga_r)
	OR (x_dis(11) AND valid AND vga_r)
	OR (x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND valid AND 
	NOT x_dis(8))
	OR (x_dis(5) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(8))
	OR (NOT x_dis(5) AND NOT x_dis(6) AND NOT x_dis(7) AND x_dis(9) AND 
	NOT x_dis(10) AND NOT x_dis(11) AND valid)
	OR (x_dis(6) AND x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND 
	NOT x_dis(11) AND valid AND x_dis(8))
	OR (x_dis(7) AND NOT x_dis(9) AND NOT x_dis(10) AND NOT x_dis(11) AND 
	valid AND x_dis(4) AND x_dis(8)));

FTCPE_vga_vsync: FTCPE port map (vga_vsync,vga_vsync_T,clk,'0',NOT reset_n,'1');
vga_vsync_T <= ((NOT y_cnt(0) AND y_cnt(1) AND y_cnt(2) AND NOT y_cnt(3) AND 
	NOT y_cnt(5) AND NOT y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND NOT y_cnt(7) AND 
	NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11) AND NOT vga_vsync)
	OR (NOT y_cnt(0) AND NOT y_cnt(1) AND NOT y_cnt(2) AND NOT y_cnt(3) AND 
	NOT y_cnt(5) AND NOT y_cnt(4) AND NOT y_cnt(6) AND NOT y_cnt(9) AND NOT y_cnt(7) AND 
	NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11) AND vga_vsync));

FTCPE_x_cnt0: FTCPE port map (x_cnt(0),'0',clk,NOT reset_n,'0','1');

FTCPE_x_cnt1: FTCPE port map (x_cnt(1),x_cnt(0),clk,NOT reset_n,'0','1');

FTCPE_x_cnt2: FTCPE port map (x_cnt(2),x_cnt_T(2),clk,NOT reset_n,'0','1');
x_cnt_T(2) <= (x_cnt(0) AND x_cnt(1));

FTCPE_x_cnt3: FTCPE port map (x_cnt(3),x_cnt_T(3),clk,NOT reset_n,'0','1');
x_cnt_T(3) <= (x_cnt(0) AND x_cnt(2) AND x_cnt(1));

FTCPE_x_cnt4: FTCPE port map (x_cnt(4),x_cnt_T(4),clk,NOT reset_n,'0','1');
x_cnt_T(4) <= NOT (((NOT x_cnt(3))
	OR (NOT x_cnt(0))
	OR (NOT x_cnt(2))
	OR (NOT x_cnt(1))
	OR (NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND 
	NOT x_cnt(7) AND NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11))));

FTCPE_x_cnt5: FTCPE port map (x_cnt(5),x_cnt_T(5),clk,NOT reset_n,'0','1');
x_cnt_T(5) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(4));

FTCPE_x_cnt6: FTCPE port map (x_cnt(6),x_cnt_T(6),clk,NOT reset_n,'0','1');
x_cnt_T(6) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4));

FTCPE_x_cnt7: FTCPE port map (x_cnt(7),x_cnt_T(7),clk,NOT reset_n,'0','1');
x_cnt_T(7) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6));

FTCPE_x_cnt8: FTCPE port map (x_cnt(8),x_cnt_T(8),clk,NOT reset_n,'0','1');
x_cnt_T(8) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(7));

FTCPE_x_cnt9: FTCPE port map (x_cnt(9),x_cnt_T(9),clk,NOT reset_n,'0','1');
x_cnt_T(9) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7));

FTCPE_x_cnt10: FTCPE port map (x_cnt(10),x_cnt_T(10),clk,NOT reset_n,'0','1');
x_cnt_T(10) <= ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND 
	x_cnt(9))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11)));

FTCPE_x_cnt11: FTCPE port map (x_cnt(11),x_cnt_T(11),clk,NOT reset_n,'0','1');
x_cnt_T(11) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND 
	x_cnt(9) AND x_cnt(10));

FDCPE_x_dis2: FDCPE port map (x_dis(2),x_dis_D(2),clk,NOT reset_n,'0','1');
x_dis_D(2) <= ((x_cnt(2) AND NOT x_cnt(6) AND x_cnt(8) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (x_cnt(2) AND x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (x_cnt(2) AND NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (NOT x_cnt(3) AND x_cnt(2) AND NOT x_cnt(5) AND x_cnt(8) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(2) AND NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(8) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(2) AND x_cnt(6) AND x_cnt(7) AND NOT x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(3) AND x_cnt(2) AND x_cnt(5) AND x_cnt(4) AND 
	NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)));

FDCPE_x_dis3: FDCPE port map (x_dis(3),x_dis_D(3),clk,NOT reset_n,'0','1');
x_dis_D(3) <= (NOT x_cnt(3) AND NOT x_cnt(10) AND NOT x_cnt(11))
	XOR ((NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(3) AND NOT x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(3) AND x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND 
	x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)));

FDCPE_x_dis4: FDCPE port map (x_dis(4),x_dis_D(4),clk,NOT reset_n,'0','1');
x_dis_D(4) <= NOT (((x_cnt(10))
	OR (x_cnt(11))
	OR (x_cnt(3) AND x_cnt(4))
	OR (NOT x_cnt(3) AND NOT x_cnt(4))
	OR (NOT x_cnt(6) AND N_PZ_299)
	OR (NOT x_cnt(7) AND N_PZ_299)
	OR (x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND 
	x_cnt(9))));

FDCPE_x_dis5: FDCPE port map (x_dis(5),x_dis_D(5),clk,NOT reset_n,'0','1');
x_dis_D(5) <= NOT (((x_cnt(10))
	OR (x_cnt(11))
	OR (NOT x_cnt(3) AND NOT x_cnt(5))
	OR (NOT x_cnt(5) AND NOT x_cnt(4))
	OR (NOT x_cnt(6) AND N_PZ_299)
	OR (NOT x_cnt(7) AND N_PZ_299)
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4))
	OR (x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND x_cnt(9))));

FDCPE_x_dis6: FDCPE port map (x_dis(6),x_dis_D(6),clk,NOT reset_n,'0','1');
x_dis_D(6) <= ((NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND 
	NOT N_PZ_299)
	OR (NOT x_cnt(5) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND 
	NOT N_PZ_299)
	OR (NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(10) AND NOT x_cnt(11) AND 
	NOT N_PZ_299)
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND 
	x_cnt(8) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND 
	NOT x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND x_cnt(6) AND 
	x_cnt(7) AND NOT x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)));

FDCPE_x_dis7: FDCPE port map (x_dis(7),x_dis_D(7),clk,NOT reset_n,'0','1');
x_dis_D(7) <= ((x_cnt(6) AND NOT x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11) AND 
	NOT N_PZ_299)
	OR (NOT x_cnt(3) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND 
	NOT x_cnt(11) AND NOT N_PZ_299)
	OR (NOT x_cnt(5) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND 
	NOT x_cnt(11) AND NOT N_PZ_299)
	OR (NOT x_cnt(4) AND NOT x_cnt(6) AND x_cnt(7) AND NOT x_cnt(10) AND 
	NOT x_cnt(11) AND NOT N_PZ_299)
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(7) AND 
	NOT x_cnt(10) AND NOT x_cnt(11) AND NOT N_PZ_299));

FDCPE_x_dis8: FDCPE port map (x_dis(8),x_dis_D(8),clk,NOT reset_n,'0','1');
x_dis_D(8) <= ((NOT x_cnt(8) AND NOT x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (NOT x_cnt(3) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(5) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(6) AND x_cnt(8) AND x_cnt(7) AND NOT x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(3) AND NOT x_cnt(5) AND x_cnt(6) AND x_cnt(8) AND 
	x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(6) AND x_cnt(8) AND 
	x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND 
	x_cnt(8) AND x_cnt(7) AND NOT x_cnt(10) AND NOT x_cnt(11)));

FDCPE_x_dis9: FDCPE port map (x_dis(9),x_dis_D(9),clk,NOT reset_n,'0','1');
x_dis_D(9) <= ((NOT x_cnt(6) AND x_cnt(8) AND x_cnt(9) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (x_cnt(8) AND NOT x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND 
	NOT x_cnt(11))
	OR (NOT x_cnt(3) AND NOT x_cnt(5) AND x_cnt(8) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (NOT x_cnt(5) AND NOT x_cnt(4) AND x_cnt(8) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(6) AND NOT x_cnt(8) AND x_cnt(7) AND x_cnt(9) AND 
	NOT x_cnt(10) AND NOT x_cnt(11))
	OR (x_cnt(3) AND x_cnt(5) AND x_cnt(4) AND NOT x_cnt(6) AND 
	x_cnt(7) AND x_cnt(9) AND NOT x_cnt(10) AND NOT x_cnt(11)));

FDCPE_x_dis10: FDCPE port map (x_dis(10),'0',clk,NOT reset_n,'0','1');

FDCPE_x_dis11: FDCPE port map (x_dis(11),'0',clk,NOT reset_n,'0','1');

FTCPE_y_cnt0: FTCPE port map (y_cnt(0),y_cnt_T(0),clk,NOT reset_n,'0','1');
y_cnt_T(0) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11));

FTCPE_y_cnt1: FTCPE port map (y_cnt(1),y_cnt_T(1),clk,NOT reset_n,'0','1');
y_cnt_T(1) <= ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(2))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(3))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(5))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(4))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(6))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(9))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(7))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(10))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(8))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(11)));

FTCPE_y_cnt2: FTCPE port map (y_cnt(2),y_cnt_T(2),clk,NOT reset_n,'0','1');
y_cnt_T(2) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1));

FDCPE_y_cnt3: FDCPE port map (y_cnt(3),y_cnt_D(3),clk,NOT reset_n,'0','1');
y_cnt_D(3) <= NOT (NOT y_cnt(3)
	XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND 
	NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))));

FDCPE_y_cnt4: FDCPE port map (y_cnt(4),y_cnt_D(4),clk,NOT reset_n,'0','1');
y_cnt_D(4) <= NOT (NOT y_cnt(4)
	XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND 
	NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))));

FTCPE_y_cnt5: FTCPE port map (y_cnt(5),y_cnt_T(5),clk,NOT reset_n,'0','1');
y_cnt_T(5) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(4));

FTCPE_y_cnt6: FTCPE port map (y_cnt(6),y_cnt_T(6),clk,NOT reset_n,'0','1');
y_cnt_T(6) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4));

FDCPE_y_cnt7: FDCPE port map (y_cnt(7),y_cnt_D(7),clk,NOT reset_n,'0','1');
y_cnt_D(7) <= NOT (NOT y_cnt(7)
	XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND 
	NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))));

FTCPE_y_cnt8: FTCPE port map (y_cnt(8),y_cnt_T(8),clk,NOT reset_n,'0','1');
y_cnt_T(8) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND 
	y_cnt(7));

FDCPE_y_cnt9: FDCPE port map (y_cnt(9),y_cnt_D(9),clk,NOT reset_n,'0','1');
y_cnt_D(9) <= NOT (NOT y_cnt(9)
	XOR ((x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND 
	y_cnt(7) AND y_cnt(8))
	OR (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND NOT y_cnt(1) AND 
	NOT y_cnt(2) AND y_cnt(3) AND NOT y_cnt(5) AND y_cnt(4) AND NOT y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND NOT y_cnt(10) AND NOT y_cnt(8) AND NOT y_cnt(11))));

FTCPE_y_cnt10: FTCPE port map (y_cnt(10),y_cnt_T(10),clk,NOT reset_n,'0','1');
y_cnt_T(10) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND y_cnt(8));

FTCPE_y_cnt11: FTCPE port map (y_cnt(11),y_cnt_T(11),clk,NOT reset_n,'0','1');
y_cnt_T(11) <= (x_cnt(3) AND x_cnt(0) AND x_cnt(2) AND x_cnt(1) AND 
	NOT x_cnt(5) AND NOT x_cnt(4) AND NOT x_cnt(6) AND NOT x_cnt(8) AND NOT x_cnt(7) AND 
	NOT x_cnt(9) AND x_cnt(10) AND NOT x_cnt(11) AND y_cnt(0) AND y_cnt(1) AND 
	y_cnt(2) AND y_cnt(3) AND y_cnt(5) AND y_cnt(4) AND y_cnt(6) AND 
	y_cnt(9) AND y_cnt(7) AND y_cnt(10) AND y_cnt(8));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-7-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-7-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              51 VCCIO-1.8                     
  2 TIE                              52 TIE                           
  3 TIE                              53 TIE                           
  4 TIE                              54 TIE                           
  5 VCCAUX                           55 TIE                           
  6 TIE                              56 TIE                           
  7 TIE                              57 VCC                           
  8 TIE                              58 TIE                           
  9 TIE                              59 TIE                           
 10 TIE                              60 TIE                           
 11 TIE                              61 TIE                           
 12 TIE                              62 GND                           
 13 TIE                              63 TIE                           
 14 TIE                              64 TIE                           
 15 TIE                              65 TIE                           
 16 TIE                              66 TIE                           
 17 TIE                              67 TIE                           
 18 TIE                              68 TIE                           
 19 TIE                              69 GND                           
 20 VCCIO-1.8                        70 TIE                           
 21 GND                              71 TIE                           
 22 clk                              72 TIE                           
 23 TIE                              73 TIE                           
 24 TIE                              74 TIE                           
 25 GND                              75 GND                           
 26 VCC                              76 TIE                           
 27 vga_hsync                        77 TIE                           
 28 vga_vsync                        78 TIE                           
 29 vga_r                            79 TIE                           
 30 vga_g                            80 TIE                           
 31 GND                              81 TIE                           
 32 vga_b                            82 TIE                           
 33 TIE                              83 TDO                           
 34 TIE                              84 GND                           
 35 TIE                              85 TIE                           
 36 TIE                              86 TIE                           
 37 TIE                              87 TIE                           
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 TIE                              89 TIE                           
 40 TIE                              90 TIE                           
 41 TIE                              91 TIE                           
 42 TIE                              92 TIE                           
 43 TIE                              93 TIE                           
 44 TIE                              94 TIE                           
 45 TDI                              95 TIE                           
 46 TIE                              96 TIE                           
 47 TMS                              97 TIE                           
 48 TCK                              98 VCCIO-1.8                     
 49 TIE                              99 reset_n                       
 50 TIE                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-7-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : FLOAT
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28