Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u_sdram_vga_top|u_lcd_top|u_lcd_driver 18 1 0 1 48 1 1 1 0 0 0 0 0
u_sdram_vga_top|u_lcd_top 18 0 0 0 47 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdbank_switch 6 0 0 0 6 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe4 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe3 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 0 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo|dcfifo_component|auto_generated 21 0 0 0 25 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_rdfifo 21 0 0 0 25 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 10 0 0 0 1 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe11 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 0 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe11 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo|dcfifo_component|auto_generated 21 0 0 0 25 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl|u_wrfifo 21 0 0 0 25 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_dcfifo_ctrl 151 0 0 0 80 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_sdramtop|module_003 31 0 9 0 16 0 0 0 16 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_sdramtop|module_002 82 0 0 0 19 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_sdramtop|module_001 22 0 0 0 21 0 0 0 0 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top|u_sdramtop 82 0 0 0 38 0 0 0 16 0 0 0 0
u_sdram_vga_top|u_sdram_2fifo_top 133 100 0 100 41 100 100 100 16 0 0 0 0
u_sdram_vga_top 24 0 0 0 44 0 0 0 16 0 0 0 0
u_CMOS_Capture 14 0 0 0 20 0 0 0 0 0 0 0 0
u_I2C_AV_Config|u_I2C_Controller 30 8 0 8 11 8 8 8 1 0 0 0 0
u_I2C_AV_Config|u_I2C_OV7670_RGB565_Config 8 0 0 0 16 0 0 0 0 0 0 0 0
u_I2C_AV_Config 2 0 0 0 10 0 0 0 1 0 0 0 0
u_system_ctrl|u_sdram_pll|altpll_component|auto_generated 3 0 0 0 6 0 0 0 0 0 0 0 0
u_system_ctrl|u_sdram_pll 2 0 0 0 5 0 0 0 0 0 0 0 0
u_system_ctrl|u_system_delay 2 0 0 0 1 0 0 0 0 0 0 0 0
u_system_ctrl 2 1 0 1 5 1 1 1 0 0 0 0 0